Circuit to find the no of ones and no of zeros in a 5 input bit stream

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dll_fpga

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hi,
i need to find the difference of no of zeros and ones in a 5 input bit stream
Please suggest a simple circuit / digital logic to achieve this
eg:
10011
gives -1
01100
gives +1
10000
gives 3
 
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Hi,

I have drawn the diagram for the circuit. The diagram is self explanatory. The salient points are.
1) minimum 3 bit counter is required to count 5 bit stream. there are separate counters for counting '0' & '1'
2) The counters are -ve edge triggered ripple counters
3) The data stream must be generated at half the frequency of that of main clock
4) The concept is that the -ve edge of pulsed clock is allowed to pass to the respective counter based upon which data is coming '0' or '1'.
5) One stage is not drawn. You can feed the result of counters to 'subtraction circuit' (can be made by full subtractors) . And get your final result.

-------
Shobhit
 

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is it possible to do this fully combinatory...without sequential circuit....also data generator need not be there...as the data is coming thrgh a standard bus...
 

Hi dll_fpga,

I dont think that you will be able to design such a circuit w/o sequential elements.
The reason is that you need to save the counts (a memory mechanism) and thus you need an FSM.
You cannot do away with the counter which is a sequential circuit.
Yes you can remove the divider if you get the required clock source.

As you are reading the data from a bus. Then in order to use the circuit shown above, you need to have a clock
source of double the frequency of the data rate of bus, which you can process to generate the pulsed clock.

thanks,
Shobhit
 

shobhit said:
I dont think that you will be able to design such a circuit w/o sequential elements.
Click to expand...
I think you're assuming the 5 bits will be received sequentially on a single input lines. I was assuming the 5 bits are received simultaneously on 5 separate input lines.

Maybe that needs to be clarified first.
 

Yes, the term "stream" possibly suggests bit serial data. But in this case, a shift register can convert it to parallel data.

Without special requirements for the implementation, I would write a behavioral description and utilize a HDL tool to synthesize the logic.
 

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