Circuit Board Layout Questions

[JFParnell]

I am a mechanical engineer that is responsible for also producing PCB drawings for manufacture. We send these drawings out with a set of gerber files to the manufacturing houses to specify what we need from our designs. Recently we have been trying to greatly improve what we specify on our drawings, as we have realized that what we were calling out was insufficient. With that being said, we are currently very wrapped up in specifying final copper trace thicknesses for our stackups. We are trying to avoid getting too much thickness as this makes SMT rework very difficult due to the large copper thickness heat sinking away the the heat and not allowing the solder to flow. We have one current design that uses two different circuit boards and stackups and are trying to specify the final copper thicknesses of each layer.

1) Stackup is a six layer board, with .062 final thickness. The board is to be IPC Class 3, which specifies a minimum plated thickness of .000787 in the vias. Layer 1 (top trace layer) is .0007 copper foil bonded with prepreg to layer2. Layer 2 and 3 are .0014 foil bonded to a core. Layer 3 is bonded to layer 4 with prepreg. Layer 4 and 5 are .0014 foil bonded to a core. Layer 5 is bonded to Layer 6 (bottom trace layer) with prepreg. Layer 6 (bottom trace layer) is .0007 thick copper foil. Vias are plated .008 diameter thru holes through all layers. The question then is what are the final layer thicknesses that are possible for each layer? I assume that all of the inner layers for this layup will be very close to the original .0014 thickness as they are not plated, but they will be slightly thinner due to the action of the press. Thus the major question is what thickness of the outer two layers will be when the plated vias get to .000787 at the center of the board.

2) Stack up is a four layer board, with .062 final thickness. The board is to be IPC Class 3, which specifies a minimum plated thickness of .000787 in the vias. Layer 1 and 2 are .00014 thick foil bonded to a .021 thick core. Layer 2 is bonded to Layer 3 with prepreg. Layer 3 and 4 are .0007 thick foil bonded to a .021 thick core. There are blind vias through layer 3 and 4 of .008 diameter, and thru hole vias through the whole board of .008 diameter. I would like to know again what are the possible copper trace thicknesses of each layer when the middle of the vias get to .000787 minimum thickness.

The electrical engineer is trying to achieve .0014 final nominal copper thickness on all of the layers, but I am not sure this is possible, especially after viewing the inspection reports on the prototype boards. We are currently seeing final thicknesses on layers up in the .00488 thick range, which is huge.

Any help with understanding what is achievable with current technology would be greatly appreciated.

JFP

 

[barry]

Specify your copper thickness and your overall board thickness and the pcb vendor will take care of the rest. Unless you're got controlled impedance, which it doesn't sound like you do, you don't have to worry too much about the layer thicknesses. I have no idea why you're seeing 4.88 mil thickness on inner layers, that doesn't sound right. Maybe you need a different vendor.

 

[JFParnell]

Specify your copper thickness and your overall board thickness and the pcb vendor will take care of the rest. Unless you're got controlled impedance, which it doesn't sound like you do, you don't have to worry too much about the layer thicknesses. I have no idea why you're seeing 4.88 mil thickness on inner layers, that doesn't sound right. Maybe you need a different vendor.

They are telling that the thick layers are due to having to plate the .008 holes to .000787 minimum thickness on the walls. The 4.88 mil layer is an outer layer, except in the case of one of the bottom two layers with the blind vias. Is 1 mil final copper thickness possible with .8 mil vias and a Class 3 board?

 

[marce]

Start with a thinner base laminate... Copper is specified in ounces or microns preferably.
You are trying to achieve a 35micron (0.035mm approx 1oz) finish on the copper layers, with 0.020mm barrel plating. Class 3 requires a minimum of 0.025mm plating down the barrel (0.020mm is not good enough). Usually start with 0.035mm copper and plate to 0.025mm gives a surface finish of 0.052mm, start with 0.018mm copper and you will get approx 0.035mm surface finish on the copper.
I don't design for re-work that's designing for failure in my book, I design a board for what the circuit needs in terms of current capacity, thermal requirements etc. All boards can be reworked regardless of final copper thickness.

For the record I have never specified or would specify any PCB with a via plating of less than 0.025mm (0.989")

 

[JFParnell]

Actually the IPC standard Class 3 calls out for a minimum of .020mm thickness with an average thickness of .025mm. Granted you are trying to achieve .025mm overall plated average, but the thin areas can go down to .020mm.

 

[marce]

You have to specify 0.025mm plating for Class 3... Not 0.020mm though otherwise you wont get a class 3 finish board. As I said I have never gone below 0.025mm plating on any board and for class 3 I often go higher, because I want my class 3 boards to be class 3. So to achieve class 3 you always have to specify 0.025 or above, was what I was getting at.