CIC filter verilog code

hi,, i am doing a project on SOFTWARE DEFINED RADIO in which i am using a CIC filter which is implemented in FPGA.And hence i need to write a verilog code for cic.can u help me with a simple code please......:-(

There are several Verilog CIC examples in previous threads, just search edaboard. I'm writing this stuff in VHDL, thus I can't give you any examples. You are welcome with specific questions related to your code, however.

// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input clk,reset;
input [7:0] x_in;
output [7:0] y_out;

parameter hold=0, sample=1;
reg state; //sample or hold states
reg [5:0] count; //count till 63 starting from 0
reg [7:0] x; //input
wire [23:0] sx; //sign extended input
reg [23:0] i0; //Integrator output section 0
reg [18:0] i1; //output section 1 under the consideration of Haugenauer's pruning
reg [13:0] i2;
reg [11:0] i2d1, c1, c0; // Integrator+COMB 0
reg [10:0] c1d1, c2;
reg [9:0] c2d1, c3;



always @(negedge clk)
begin : FSM // finite state machine
case (state)
hold : begin
if (count<63) // setting states for downsampling
state <= hold;
else
state <=sample;
end
default:
state <= hold;
endcase
end

assign sx={{16{x[7]}},x_in};


// Integrator
always @(posedge clk)begin
if(reset) begin
i0 <= 24'd0;
i1 <= 19'd0;
i2 <= 14'd0;
x <= 8'd0;
end
else
x <= x_in;
i0 <= i0+sx;
i1 <= i1+i0[23:7];
i2 <= i2+i1[18:5];
case (state) //downsample
sample : begin
c0 <= i2[13:1];
count <= 0; //reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end

// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;
c1 <= c0-i2d1;
c1d1 <= c1[11:1];
c2 <= c1[11:1]-c1d1;
c2d1 <= c2[10:1];
c3 <= c2[10:1]-c2d1;
end

assign y_out=c3[9:2];
endmodule

Test bench
`timescale 1ns/1ps
module test;
reg clk,reset;
reg [7:0] x;
wire [7:0] y;

cicdecim64 cic (x,y,clk,reset);
initial begin
x <=8'd1;
clk<=1'b0;
reset <= 1'b0;
#4 reset=~reset;
#5 reset=~reset;

end
always
#4 clk=~clk;

endmodule

I found this cic code from previous threads.there are no errors when complied.but there is no change in the output y_out variable.Can u just help me out with this please?

cicdecim64 has serious implementation errors. The comb section must be run at the downsampled rate, under the condition if (state == sample).

P.S.: I just found, that the code is a slightly modified copy of the CIC Verilog code in Digital Signal Processing with FPGA by U. Meyer-Baese.

But in the original code, except for different decimation factors and word width, the comb section is operated at the low rate.


Conclusion better refer to a good text book.

FvM said:

There are several Verilog CIC examples in previous threads, just search edaboard. I'm writing this stuff in VHDL, thus I can't give you any examples. You are welcome with specific questions related to your code, however.

Click to expand...

hai
we got the vhdl code for NCO....so can u help us with vhdl code for cic filter ??
thanks

FvM said:

There are several Verilog CIC examples in previous threads, just search edaboard. I'm writing this stuff in VHDL, thus I can't give you any examples. You are welcome with specific questions related to your code, however.

Click to expand...

Can you give me the code of CIC filter in Vhdl...I am learning on a topic "implementing cic filter for software defined radio applications"...Please if you coiuld reply asap.