Choosing PLL: ADPLL or Fractional N or Integer N

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Hi experts,

I have the following requirements for my frequency synthesizer PLL

center frequency= 700MHz, channel bandwidth=300KHz
channel switch time<=100us
Phase noise<= -100dBc/Hz@ 1MHz offset

I want to make the PLL as low power as possible (<700uW). Which is the most suitable architecture:
All digital PLL
Integer N PLL (Type 1 or Type2)
Fractional N PLL

With type2 integer N PLL: Loop BW=1/10th of channel BW=30KHz. This makes it difficult to achieve channel switch time of <100us
 

If this PLL will work with VDD=3V, the current consumption will be around 230uA !!
I wish you good luck..
 

what do you mean by "channel bandwidth"?

what are the number of frequency steps, start and stop frequency. Are you stuck with a specific reference frequency?

you really don't care what the phase noise is at say 10 kHz offset? It can be really bad there?
 

Hi BigBoss,

Why is VDD=3V make it low power=230ux3=690uW? What is the architecture? Will channel switch time=100us be satisfied?

- - - Updated - - -

Hi biff44,

By channel BW I mean channel spacing =1MHz i.e. PLL has to generate frequencies 670MHz, 671MHz....729MHz, 730MHz. I dont care about phase noise at 10khz offset. I want the phase noise to be -100dBc at 1MHz offset
 

Perhaps <700 mW is realistic.

Why <700uW ? this would require nano volt logic

Consider power to drive 800MHz at 1V is equiv. to 20 Ohms load for 10pF single load. With many signals in VCO, mixer and prescaler , this requirement is unrealistic.
 

analog_chip said:
Hi BigBoss,
Why is VDD=3V make it low power=230ux3=690uW? What is the architecture? Will channel switch time=100us be satisfied?
Click to expand...
Let's change if you would as 1V..
The current consumption will be 700uA !!
Even a CMOS divider consumes much more than this.
If you intend to see a good Phase Noise@1MHz, your VCO must be quiet and your PLL type is absolutely Integer type because PN performance of Fractional ( Sigma Delta ) PLL is worse then Integer equivalent @ far off-set frequencies.
But VCO PN is more dominant @ that frequency ( in general applications ).
Lowest Power PLL ( it was a academic work ) that I have ever seen was consuming at least 3mA.
Reconsider your specifications...
100us switching time is possible with a wideband Loop Bandwidth ( all Loop Filter+VCO+Charge Pump+PFD etc.)
 

How does the loop bandwidth and switch time related? Any empirical or amalytical expression?
 

There are numerous text books on the topic but I assume you need/want hands-on Why not d/l the free software from Analog Devices SimPLL. You can play with all sorts of settings and get a feeling for what happens when you alter loop filter vs. switching time and spur supression.
If you really want to read some basic stuff, Digital PLL frequency synthesizers by Ulrich Rohde An old but still valid book about basic PLL design.
 

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