Chip voltage and temperature variation

IR drop in package. IR drop in chip power/ground mesh etc

Could you please tell me how to design a test to prove it?

IR drop is reasonable, but I would first suspect something with the IOs or with the ESD protection. I assume you have another supply at 2.5V or 3.3V. The IO might require both supply voltages to be in acceptable range to turn "on". The meaning of turn on can be anything. Some IO cells have power on control structure. Some have ESD protection that takes the difference between the two supplies. Good luck hunting the issue!

First you have to declare what "fail" means. For what? I/O drive strength?
At-speed pattern? Input data:clk skew / eye?

Then you would start doing things like reducing test data rate to see if
raw stage delay vs clock period is the thing. Skew the clocks and see if
the pattern "gets right". Review detail data for parametrics to see if it's
a "cliff" or just more, predictable rolloff of "whatever".

It seems like a skew in bias tracking .

ThisIsNotSam said:

IR drop is reasonable, but I would first suspect something with the IOs or with the ESD protection. I assume you have another supply at 2.5V or 3.3V. The IO might require both supply voltages to be in acceptable range to turn "on". The meaning of turn on can be anything. Some IO cells have power on control structure. Some have ESD protection that takes the difference between the two supplies. Good luck hunting the issue!

Click to expand...

dick_freebird said:

First you have to declare what "fail" means. For what? I/O drive strength?
At-speed pattern? Input data:clk skew / eye?

Then you would start doing things like reducing test data rate to see if
raw stage delay vs clock period is the thing. Skew the clocks and see if
the pattern "gets right". Review detail data for parametrics to see if it's
a "cliff" or just more, predictable rolloff of "whatever".

Click to expand...

I have lower the chip DVDD LDO to 0.7mv. I provide the digital supply from the DVDD PIN so I could adjust the voltage from the external supply. What I said 1.0v and 0.99v is provide from the external supply. The abnormal I means CPU run out of control. Because I am digital engineer, I care about digital logic function.

dick_freebird said:

First you have to declare what "fail" means. For what? I/O drive strength?
At-speed pattern? Input data:clk skew / eye?

Then you would start doing things like reducing test data rate to see if
raw stage delay vs clock period is the thing. Skew the clocks and see if
the pattern "gets right". Review detail data for parametrics to see if it's
a "cliff" or just more, predictable rolloff of "whatever".

Click to expand...

The fail I means CPU run out of control. Because I am digital engineer, I care about digital logic function. I provide the digital supply from the DVDD PIN so I could adjust the voltage from the external supply.

So maybe your memory bus has gone unreliable when your
output levels drop. How are we to know? Debug skillz time.

some STM32's run down to 1.08V. Is it a

MSP430L092 0.9V MCU​

Show your device datasheet

D.A.(Tony)Stewart said:

some STM32's run down to 1.08V.
Show your device datasheet

Click to expand...

I understood that this is a custom chip designed by the OP

ThisIsNotSam said:

I understood that this is a custom chip designed by the OP

Click to expand...

Good point. I overlooked at that time. perhaps the problem is condensation

The COD is batter then the QFN package. It have 20mV lower than the QFN for both DVDD and DVDD_RAM. Does this means It is IR Drop problem? Can there any experiment I can do?

20mV is really not that much. Can you check the VDD/GND on a scope as the chip runs to see if there are large bounces?

You might look to the idealness (or the lack) of decoupling
capacitors, their quality and how large their wire-loop to the
VDD and VSS pins is. COB could be great or lousy depending
if the layout had this as an interest or an afterthought (or no
thought at all). Similarly package sockets can add a half-turn
inductance (or not) depending on lead form.

One blind-stab experiment would be to make the best PCB you
can imagine, for a best-part-attach with best practice decoupling
and other SI/PI interests, and measure that before you try too
hard getting the lipstick on the pig-at-hand test article. Take a
step back, what would you do if this was your top care-about
and you needed to demonstrate capability?

Your minimum-working-Vdd is a budget including ohmic droop,
supply inductances at edges, ground bounce, timing sensitivities
and so on. 20mV is nothing - until you get 10mV away from
"the cliff".

Time to break out that Acme Troubleshooting Kit and make
like Mr. Coyote*. There's a cliff around there somewhere.
Maybe two.

*Can't be the Roadrunner because his stuff always just works,
without trying.

Normally the limiting factor in low voltage CMOS is the RdsOn*C time constant delay effects on critical races. Lowering voltage raises the RdsOn*Coss time constant. But since temperature also has a coefficent for RdsOn which has no effect on your results, then some other fault must exist that is voltage dependent such as AC voltage gain for an oscillator. Yet that too is thermally dependent. This is why I guessed that there is some imbalance or skew in bias tracking of analog functions for self-bias references below some critical level.

Otherwise who knows what you have except Mr Coyote, the cartoon character who is teaching you about Murphy's Law. ( and we all know digital circuits are just analog ones with such high SNR. they will never make errors in your designed lifetime )