Chip Edge and Chip Guard Ring

Dear Friends,

As you may know that, the chip edge has to connect to some voltage level or the DRC will report the error, so I have done my Chip edge as below:



as illustrated, the chip edge has been connected to the LNA_GND, I hope this should be all right.

And furthermore, I have simply given the chip guard rings as below:



Thanks so much again for your opinions.

"Has to", must be foundry and/or flow specific because
in 30+ years of doing IC design and layout I have yet
to encounter such a requirement. But I play in kooky
SOI foundries / flows pretty much.

I would pick the quietest negative potential and probably
resistor-degenerate the ring bias to minimize ground
pumping by fast signals (the edge seal is a big antenna).
Which

Those "guard rings" look like simple metal bussing to me,
while guardrings imply silicon P+ and N+ regions with
structure intended to extract substrate currents (ohmic)
and loose minority carriers (biased depletion regions).

I think you want to understand the intent of these structures
and find any foundry guidance as far as approved schemes
(probably a "scribe" PCell in the PDK?).