BartlebyScrivener
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With systemverilog, are there neat ways to check designs, for example, get a test bench to check values on output ports against a given set of numbers?
At the moment I just write normal always blocks to simulate my designs, and then run them for x amount of seconds, and look at the waveforms, but following through loads of waveforms, manually checking packets come out the right port etc is making my eyes wobble!
Many thanks.
- - - Updated - - -
I just found the answer to my own question. The following site appears full of information.
http://www.testbench.in/TS_08_SELF_CHECKING_TESTBENCHS.html
At the moment I just write normal always blocks to simulate my designs, and then run them for x amount of seconds, and look at the waveforms, but following through loads of waveforms, manually checking packets come out the right port etc is making my eyes wobble!
Many thanks.
- - - Updated - - -
I just found the answer to my own question. The following site appears full of information.
http://www.testbench.in/TS_08_SELF_CHECKING_TESTBENCHS.html