Check my VHDL code for actel FPGA

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;  -- this library should contain "-" functions for logic_vector's but statement did not work 

entity UART_CLK is
	port (
		clk : in std_ulogic;
		rst : in std_ulogic;
		CLK384 : out std_ulogic);
end UART_CLK;				   

architecture behavioral of UART_CLK is
	signal clkDiv : INTEGER RANGE 0 TO 255;
	signal CLKt : std_ulogic;
	constant baudDivide : INTEGER RANGE 0 TO 255 := 130;
begin
	process (clk, rst)
	begin
		if (rst = '1') then
			clkDiv <= baudDivide;
			CLKt <= '0';
		elsif (clk = '1' and clk'event) then
			if (clkDiv = 0) then
				clkDiv <= baudDivide;
				CLKt <= not CLKt;
			else
				clkDiv <= clkDiv - 1;
			end if;
		end if;
	end process;
	CLK384 <= CLKt;
end behavioral;

library IEEE;
use IEEE.std_logic_1164.all;      
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity UART_CLK is 
port ( 
clk : in std_ulogic; 
rst : in std_ulogic; 
CLK384 : out std_ulogic 
); 
end UART_CLK; 
architecture behavioral of UART_CLK is 
signal clkDiv : std_logic_vector(7 downto 0); 
signal CLKt : std_ulogic; 
constant baudDivide : std_logic_vector(7 downto 0) := X"82"; 

begin 
process (clk, rst) 
begin 
if (rst = '1') then 
  clkDiv <= baudDivide; 
  CLKt <= '0'; 
elsif (clk = '1' and clk'event) then 
  if (clkDiv = X"00") then 
    clkDiv <= baudDivide; 
    CLKt <= not CLKt; 
  else 
    clkDiv <= clkDiv - 1; 
  end if; 
end if; 
end process; 

CLK384 <= CLKt; 
end behavioral;