check certain string from continuous input: Verilog

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beginner_EDA

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Hello Everybody,

I am receiving continuous input in hex format (of corresponding ASCII character) and I have to check certain strings (which is of bigger length. lets's say "Hello How are you") out of it and then trigger some action in verilog. But I don't know how to do that.

Could anybody please help?
 

ASCII character 8-bit wide by N entry shift register, a loadable string register, a big mask comparator to match the loaded string with the input string. That's probably the simplest implementation, but it may not be the most resource efficient if the string becomes very large.

Other implementations that are similar to software implementations of searches (where you compare byte by byte and reset when matches don't occur) are much more complex to implement and would require running the logic at a much higher rate than the continuous input data to keep up.
 
ads-ee said:
ASCII character 8-bit wide by N entry shift register, a loadable string register, a big mask comparator to match the loaded string with the input string.
Click to expand...
Hi,
Actually I have 4 bit continuous data stream at 250 MHz and I want to check MAC Address of both destination(48 bit) and source(48 bit) which is together of 96 bit long before starting the payload.
This is how I tried to check:
Code Verilog - [expand]
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input [3:0] ENET0_RX_DATA;
output [3:0] payload;
reg [3:0] input_data [0:23];
reg [4:0] index = 0;
reg [95:0] string_check = 0;
reg trigger_for_payload = 0;
 
 
    always @ (posedge test_250_mhz)
        begin 
                index <= index + 1;
                    if (index > 23)
                        begin
                            index <= 0;
                        end
                input_data[index] <= ENET0_RX_DATA;
                    
        end
        
    always @ (posedge test_250_mhz)
        begin
                if (index == 0)
                    begin
                      
                        string_check <= {input_data[0], input_data[1], input_data[2], input_data[3], input_data[4], input_data[5], input_data[6], input_data[7], 
                        input_data[8], input_data[9], input_data[10], input_data[11], input_data[12], input_data[13], input_data[14], input_data[15],
                        input_data[16], input_data[17], input_data[18], input_data[19], input_data[20], input_data[21], input_data[22], input_data[23]};
                    end
                        if (string_check == 0xe0db44d6855f0007edfe8f10) // 96 bit known source and //destination address
                            begin
                                trigger_for_payload <= 1;
                            end
                    
                end
        end
 
 
always @ (posedge test_250_mhz)
    begin
                if (trigger_for_payload == 1) 
                   begin
                           payload <= ENET0_RX_DATA
                   end
        end


but I couldn't understand how to rotate/shift at the same time while comparing the string?
 

beginner_EDA said:
but I couldn't understand how to rotate/shift at the same time while comparing the string?
Click to expand...
The problem you are having looks to be with how to pipeline a design.

Currently you are implementing each function that is required, but as individual functions, which must now interact in a pipeline.

You are using an index to demultiplex, when you should just use a shift register. Then you had registers holding values for string_check, trigger_for_payload, and payload, but none of them are fed from pipeline registers to align what they are each doing. e.g. Unless ENET0_RX_DATA doesn't start outputting the payload for what looks like 2 clock cycles you'll be sending the payload missing the first two pieces of data, because you didn't delay the data to match the control pipeline of string_check and trigger_for_payload.

Do you have a testbench? You should write one if you don't have one. And post both if you have problems you don't understand or can't solve.
 

ads-ee said:
The problem you are having looks to be with how to pipeline a design.
Click to expand...
Hi this seems to be very complicated.

Can I use state machine for this purpose?
I tried in this way but not sure whether this is correct way or not.
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// string to check from 4 bit continuous input:  0xe0db44d6855f0007edfe8f10
// once this string(MAC Address of SRC and DST) identified,  start payload.
 
 
localparam [4:0] IDLE        = 5'd0;
localparam [4:0] STATE_0     = 5'd1;
localparam [4:0] STATE_1     = 5'd2;
localparam [4:0] STATE_2     = 5'd3;
localparam [4:0] STATE_3     = 5'd4;
localparam [4:0] STATE_4     = 5'd5;
localparam [4:0] STATE_5     = 5'd6;
localparam [4:0] STATE_6     = 5'd7;
localparam [4:0] STATE_7     = 5'd8;
localparam [4:0] STATE_8     = 5'd9;
localparam [4:0] STATE_9     = 5'd10;
localparam [4:0] STATE_10    = 5'd11;
localparam [4:0] STATE_11    = 5'd12;
localparam [4:0] STATE_12    = 5'd13;
localparam [4:0] STATE_13    = 5'd14;
localparam [4:0] STATE_14    = 5'd15;
localparam [4:0] STATE_15     = 5'd16;
localparam [4:0] STATE_16     = 5'd17;
localparam [4:0] STATE_17     = 5'd18;
localparam [4:0] STATE_18     = 5'd19;
localparam [4:0] STATE_19     = 5'd20;
localparam [4:0] STATE_20     = 5'd21;
localparam [4:0] STATE_21     = 5'd22;
localparam [4:0] STATE_22     = 5'd23;
 
 
input [3:0] ENET0_RX_DATA;
output [3:0] payload;
reg     [4:0]   state;
reg     trigger_for_payload;
 
always @ (posedge test_250_mhz or posedge clock_reset)
begin
    if(clock_reset)
    begin
        state           <= IDLE;
    end
    else
    begin
        case(state)
        IDLE:
        begin
            if(ENET0_RX_DATA == 0xe)
                begin
                    state <= STATE_0;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_0:
         begin
            if(ENET0_RX_DATA == 0x0)
                begin
                    state <= STATE_1;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        
       
        STATE_1:
         begin
            if(ENET0_RX_DATA == 0xd)
                begin
                    state <= STATE_2;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_2:
         begin
            if(ENET0_RX_DATA == 0xb)
                begin
                    state <= STATE_3;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_3:
        begin
            if(ENET0_RX_DATA == 0x4)
                begin
                    state <= STATE_4;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_4:
         begin
            if(ENET0_RX_DATA == 0x4)
                begin
                    state <= STATE_5;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_5:
         begin
            if(ENET0_RX_DATA == 0xd)
                begin
                    state <= STATE_6;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_6:
        begin
            if(ENET0_RX_DATA == 0x6)
                begin
                    state <= STATE_7;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_7:
         begin
            if(ENET0_RX_DATA == 0x8)
                begin
                    state <= STATE_8;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_8:
         begin
            if(ENET0_RX_DATA == 0x5)
                begin
                    state <= STATE_9;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_9:
         begin
            if(ENET0_RX_DATA == 0x5)
                begin
                    state <= STATE_10;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_10:
         begin
            if(ENET0_RX_DATA == 0xf)
                begin
                    state <= STATE_11;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_11:
         begin
            if(ENET0_RX_DATA == 0x0)
                begin
                    state <= STATE_12;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_12:
         begin
            if(ENET0_RX_DATA == 0x0)
                begin
                    state <= STATE_13;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_PW_13:
        begin
            if(ENET0_RX_DATA == 0x0)
                begin
                    state <= STATE_14;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_14:
         begin
            if(ENET0_RX_DATA == 0x7)
                begin
                    state <= STATE_15;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
        STATE_15:
         begin
            if(ENET0_RX_DATA == 0xe)
                begin
                    state <= STATE_16;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end  
      STATE_16:
       begin
            if(ENET0_RX_DATA == 0xd)
                begin
                    state <= STATE_17;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_17:
       begin
            if(ENET0_RX_DATA == 0xf)
                begin
                    state <= STATE_18;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_18:
       begin
            if(ENET0_RX_DATA == 0xe)
                begin
                    state <= STATE_19;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_19:
       begin
            if(ENET0_RX_DATA == 0x8)
                begin
                    state <= STATE_20;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_20:
       begin
            if(ENET0_RX_DATA == 0xf)
                begin
                    state <= STATE_21;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_21:
       begin
            if(ENET0_RX_DATA == 0x1)
                begin
                    state <= STATE_22;
                end
            else
                begin
                    state <= IDLE;
                end
            
        end
      STATE_22:
       begin
            if(ENET0_RX_DATA == 0x0)
                begin
                    trigger_for_payload <= 1;
                end
            
            
        end
        default:
        begin
            state <= IDLE;
        end
        endcase
    end
end
 
always @ (posedge test_250_mhz)
    begin
                if (trigger_for_payload == 1) 
                   begin
                           payload <= ENET0_RX_DATA
                   end
        end
 
Last edited:

Such a simple state machine is not the solution. You can have a "false start" just before the correct sequence. The state machine can then be in some other state than "IDLE" when the first wanted data arrives. In software, it is common to have complex state machines for this task. Look at "lexical analyzers". "flex" is one example.

For hardware, the shift register+comparators suggested by ads-ee is a much simpler solution.
 

It's said that the "continuous data stream" is ethernet data. So packet respectively frame synchronization takes place before the MAC fields. Any state/index counter has to refer to it.
 

FvM said:
It's said that the "continuous data stream" is ethernet data. So packet respectively frame synchronization takes place before the MAC fields. Any state/index counter has to refer to it.
Click to expand...
Hi FvM,
I have udp data stream. Can I use "udp length field" and also the "frame length size" together for synchronization of frames by setting counter depending on those 2 parameters?
 

beginner_EDA said:
Hi this seems to be very complicated.

Can I use state machine for this purpose?
Click to expand...

I would avoid using a state machine altogether. As you are finding out it's much more complicated to do it the "software way" in HDL.

The last design I received UDP data, the GEMAC that we were using output a data valid signal as I recall. I edge detected the data valid and used that to start a counter for the frame. I used the count value to determine which part of the header I was at and a shift register to turn the incoming data into parallel data. In your case it would turn the 4-bit data into 48-bit source/destination addresses.

Basically all I had were a counter, a shift register, pipeline registers to align (delay) signals, and a bunch of other registers and compare logic to make decisions like is this a VLAN etc. The only "state" information in the design was the counter and the control of when it finished counting and resetting back to 0.
 

Hi
sorry but I am not able to formulate code for shift register in this case.
could you please provide some hints.
 

beginner_EDA said:
Hi
sorry but I am not able to formulate code for shift register in this case.
could you please provide some hints.
Click to expand...

Here is an example of a byte shift register that can shift 32 bytes

Code Verilog - [expand]
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reg [7:0] my_array [0:31]; // 32-element array of bytes
 
always @ (posedge clk) begin
  // shift register code
  for (i=0;i<32;i=i+1) begin
    if (i==0) begin
      my_array[i] <= input_byte;
    end else begin
      my_array[i] <= my_array[i-1];
    end
  end
end
// the above is the equivalent of...(with loop unrolled)
always @(posedge clk) begin
  my_array[0] <= input_byte;
  my_array[1] <= my_array[0];
  //...
  my_array[31] <= my_array[30];
end
// another cumbersome method...
always @ (posedge clk) begin
  // note ... means there are a lot of my_array[*] in between, that I'm too lazy to write out
  {my_array[31], my_array[30], .... , my_array[1], my_array[0]} <= {my_array[30], ... , my_array[0], input_byte};
end
 
ads-ee said:
Here is an example of a byte shift register that can shift 32 bytes
Click to expand...
Thanks for the code.
I have one question according to this:
I am not sure if I can check my string (0xe0db44d6855f0007edfe8f10 // 96 bit known source and destination address)
like below and set trigger:
Code Verilog - [expand]
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always @ (posedge clock)
begin
        if (my_array == my_string)
            begin
                trigger_for_payload <= 1;
            end
                        
end

and reset of index 0,1, ...31 is not needed?
Note: Here my_array mean {my_array[0], my_array[1], ...my_array[31]} and assuming my_string is of same size of my_array.
 
Last edited:


Drats, I forgot about you wanting to compare that string of yours to a 96-bit value.

Then you should perform the shift as follows using the same example shift register of bytes with 32 deep shift register.
Code Verilog - [expand]
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localparam data_width = 8;
localparam shift_leng = 32;
reg [data_width*shift_leng-1:0]  shift_reg;
 
// most significant byte is in the highest bits (i.e. the first value
// that was shifted in).
always @ (posedge clk) begin
  shift_reg[data_width-1:0] <= input_data[data_width-1:0];
  for (i=1;i<shift_leng;i=i+1) begin
    shift_reg[data_width*i +:data_width] <= shift_reg[data_width*(i-1) +:data_width];
  end
end
 
// then the comparison is simply
if (shift_reg == 256'h1234_1234_1234_1234_1234_1234_1234_1234) begin
  // code that does something when shift_reg content matches.
end

I didn't post this code the first time because I thought the slicing might confuse you, as it may not necessarily look like a shift register to a novice when written like this.

The previous code would have required a compare like this:
Code Verilog - [expand]
1

{my_array[31], my_array[30]....my_array[1],my_array[0]} == 256'h1234_1234_1234_1234_1234_1234_1234_1234
 
Try modular appoach, first make a FIFO register of the length of bytes u need to compare, on every byte updation compare the FIFO register with required bytes, FSM is an efficient and systematic way of doing it, u should give it a try, I did the same kind of thing with UART, FIFO register worked for me
your satates may b, if(header_match) nstate
if(msb_match) n state etc
 


Hi,
I tried FSM as mentioned in post #5 of this thread but unfortunately I didn't get expected result.
Could you please post the major part of code.
 

beginner_EDA said:
Hi,
I tried FSM as mentioned in post #5 of this thread but unfortunately I didn't get expected result.
Could you please post the major part of code.
Click to expand...

fouwad was using a UART === SLOW stuff. You are trying to work with Ethenet UDP frames. If you don't mind increasing the latency go ahead and use an FSM with a store and forward buffer to store UDP frames while you parse the header using an FSM.

I've already said you should use a pipelined approach as that results in the smallest amount of latency and is very easy to implement (once you understand the concept of pipelining). I've used UDP in multiple projects and never once used an FSM to extract the headers and route the packets.
 
ads-ee said:
Drats, I forgot about you wanting to compare that string of yours to a 96-bit value.

Then you should perform the shift as follows using the same example shift register of bytes with 32 deep shift register.
Click to expand...
Hi, Thanks. String checking is working using this pipeline method.

For next step to extract payload and synchronize the UDP Frame. I tried this way:

Code Verilog - [expand]
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// payload starts after 42 byte header. Frame = 14 byte, IP = 20 byte, UDP = 8 byte.
// and I am checking just first 12 byte of Frame header which is combination of source(6 byte) and destination(6 byte) //MAC Address. This means my payload must start after 30 byte once string is checked.
 
// For Frame synchronization, I am extracting UDP Length field and assigning to a counter as:
// counter <= UDP Length field - 8; 
// and decrementing counter and once counter is zero start new Frame (string check)
 
reg trigger = 0;
reg [95:0] string_check = 0;
reg [3:0] payload;
reg [3:0] extract_length [51:54];
reg trigger_reset = 0;
reg [15:0] count = 0;
reg [7:0] ct_extract_leng = 0;
 
reg [7:0] count_sec = 0;
 
localparam data_width = 4;
localparam shift_leng = 24;
reg [4:0] i = 0;
 
 
reg [data_width*shift_leng-1:0]  shift_reg;
 
// most significant byte is in the highest bits (i.e. the first value
// that was shifted in).
always @ (posedge test_250_mhz) 
begin
  shift_reg[data_width-1:0] <= ENET0_RX_DATA;
      for (i=1;i<shift_leng;i=i+1) 
          begin
             shift_reg[data_width*i +:data_width] <= shift_reg[data_width*(i-1) +:data_width];
          end
            end
            
 
 
// then the comparison is simply
if (shift_reg == 96'h0070DEFFF8010EBD556DF8F5)
  // code that does something when shift_reg content matches.
      begin
        trigger <= 1;   
                
      end
      
      if (trigger_reset == 1)
            begin
                trigger <= 0;   
            end
 end 
 
 
    // to extract payload length from UDP length field. UDP Payload length field is 26 byte after string check is done. // i.e. 52 nibble. but there is one register delay. So, I took 51, 52, 53, 54 nibble.  
    always @ (posedge test_250_mhz)
        begin
              if (trigger == 1)
                  begin
                  
                      ct_extract_leng <= ct_extract_leng + 1;
                        if ((ct_extract_leng > 50) && (ct_extract_leng < 55))
                            begin
                                
                                        extract_length [ct_extract_leng] <= ENET0_RX_DATA;
                            end
                                    
                                    if (ct_extract_leng > 54)
                                              begin
                                                    ct_extract_leng <= 0;
                                              end
                    end 
        end  
        
    //  resetting the Frame for Frame synchronization         
    always @ (posedge test_250_mhz)
        begin
        count <= {extract_length[51], extract_length[52], extract_length[53], extract_length[54]} - 8 ;
         count <=  count - 1 ;      
                
                    if (count == 0)
                        begin
                            trigger_reset <= 1;
                            
                        end
                    else
                        begin
                            trigger_reset <= 0;                                             
                        end
                                              
                        
                end
 
 
                
    // Taking the payload data          
    always @ (posedge test_250_mhz)
        begin
              if (trigger == 1)
                  begin
                        count_sec <= count_sec + 1; 
                            if (count_sec > 60)
                                begin
                                    Rx_fifo_write <= 1;
                                    payload <= ENET0_RX_DATA;
                                end
                            else
                                begin
                                    Rx_fifo_write <= 0;
                                    count_sec <= 0;
                                end
 
                  end
        end


but I didn't get anything in payload. What's wrong here?
 
Last edited:

Do you have a testbench to drive this code snippet?

How about providing the testbench and code that can be simulated, and I can try taking a look at it.

Here is another case of using the wrong structure to do something that is inherently a simple shift register.
Code: 
if ((ct_extract_leng > 50) && (ct_extract_leng < 55)) begin
  extract_length [ct_extract_leng] <= ENET0_RX_DATA;
end
This is creating a set of four 4-bit registers that are being indexed using a counter. So the code has to be logic that does the following:
Code: 
extract_length[51] <= (ct_extract_leng == 51) ? ENET0_RX_DATA : extract_length[51];
if it was coded like a shift register there would only be a shift enable when ct_extrat_leng is between 50 and 55 and the extract_length would have the same data as you are getting now. The way you are approaching the problem is very software like with all the indexing.
 

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