LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY updown_tb IS
END ;
ARCHITECTURE updown_tb_arch OF updown_tb IS
SIGNAL y : std_logic_vector (3 downto 0) ;
SIGNAL rst : std_logic ;
SIGNAL disp_cntrl : std_logic_vector (3 downto 0) ;
SIGNAL clk : std_logic ;
SIGNAL s : std_logic_vector (7 downto 0) ;
SIGNAL dir : std_logic ;
COMPONENT updown
PORT (
y : out std_logic_vector (3 downto 0) ;
rst : in std_logic ;
disp_cntrl : out std_logic_vector (3 downto 0) ;
clk : in std_logic ;
s : out std_logic_vector (7 downto 0) ;
dir : in std_logic );
END COMPONENT ;
-- Clock period definition
constant clk_period : time := 20 ns;
BEGIN
DUT : updown
PORT MAP (
y => y ,
rst => rst ,
disp_cntrl => disp_cntrl ,
clk => clk ,
s => s ,
dir => dir ) ;
clk_process :process
begin
for Z in 1 to 10000 -- i like to use a loop that ends at some point
loop
clk <= '1' ;
wait for clk_period/2;
clk <= '0' ;
wait for clk_period/2;
end loop;
wait;
end process;
--clk_process :process -- if you want an endless clock then use this
-- begin
-- clk <= '1' ;
-- wait for clk_period/2;
-- clk <= '0' ;
-- wait for clk_period/2;
-- end process;
signals :process
begin
rst<='1';
wait for clk_period;
rst<='0';
dir<='1';
-- do what you want here
-- you can use :
-- wait for 100 ns; wait for 1 us; wait for 100 ps;
-- wait until falling_edge(any_signal);
-- wait until rising_edge(any_signal);
-- wait until signal_name=value;
wait;
end process;
END ;