lnexp
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hi,all.
I'm designing the a low-power pll frequency synthesizer，the fout=2.4GHz,
now the cp is designed, and who could told me what else should be simulated except the static and dynamic current.
thx.
PS:the fref=16MHz,the structure is the cp with an active amplifier(rail to rail)，the GBW is 50MHz(≥3*16MHz)，but when i replace it by 100MHz,the static and dynamic current is matching.i think the GBW is not enough,but why it seems work smoothly?
I'm designing the a low-power pll frequency synthesizer，the fout=2.4GHz,
now the cp is designed, and who could told me what else should be simulated except the static and dynamic current.
thx.
PS:the fref=16MHz,the structure is the cp with an active amplifier(rail to rail)，the GBW is 50MHz(≥3*16MHz)，but when i replace it by 100MHz,the static and dynamic current is matching.i think the GBW is not enough,but why it seems work smoothly?