Charge-pump in RFID and high VDD tolerance of transistors in LDO circuit.

Hi,
My question is regarding charge-pump which is used to salvage current from RF signal to power an RFID circuit.
My understanding is, because the current must continue to be available even when there is a small gap in the RF signal, the charge pump must charge its load capacitor up to a voltage which is higher than the normal VDD used for the rest of the circuit. Now, most of the circuit (including the digital parts) will get power supply from a regulated voltage output of an LDO. But what about the LDO itself? how do people make sure that LDO circuit wont be broken as it will be driven by a voltage much higher than the standard VDD for the particular process?
Any pointer to an example implementation will be much appreciated.
Thanks in advance.

Many PDKs offer I/O cells for signal interfacing from/to higher voltages than the core supply voltage. These I/O cells contain transistors with higher voltage ratings, due to thicker gate oxide thickness, and using larger widths and lengths than the corresponding minimum values for core transistors.

If this "high voltage" option is available, you can use such transistors in the core region, too.