Changeable ps Level Delay Generation

[nadd]

Hello all,

I'm trying to sample pulses with an ADC, but the pulses are too narrow for my ADC's sample speed(100Msamples/s). Pulses' widths are about 700ps. I can only capture one sample from inside of a pulse and it's periodic.

I'm thinking of using multi pulses to get the shape of one pulse by externally triggering the ADC with adding delays on the clock source of pulses. For example, 50ps delay for the first pulse, then 100ps for the second, 150ps for the third,... till 700ps delay and reset. So, every time I will sample from different points(not periodic), then I will combine them.

My question is how can I generate ps level delays and change them on every rising edge of the clock source? Is it possible? Maybe I can use counters to change delays. Also, are FPGAs can handle it? If so, can Basys 3 do that?

 

[KlausST]

Hi,

if the pulses come periodically one could use a PLL with an output frequrncy of 255/256 for example, so over 256 loops you get detailed infirmation about the waveform.

Klaus

 

[nadd]

Hi,

if the pulses come periodically one could use a PLL with an output frequrncy of 255/256 for example, so over 256 loops you get detailed infirmation about the waveform.

Klaus

Hi Klaus,

Thank you so much for the suggestion. Sounds very good.

I'm not familiar with PLLSs, so I have been searching to understand and do what you suggest. But, I couldn't figure it out how can I use output frequency of 255/256? Using a divider?

 

[dick_freebird]

If you are after amplitude information then at that narrow
a pulse, you may find that attaching -anything- corrupts
the signal waveshape and crest.

If you have handy a track/hold amp that can pass the signal
clean, then you could play with strobe timing, find the point
of maximum value on a known-amplitude reference signal
(yeah, good luck there too), derive a "cal constant" and use
the "found peak". You could also "find" the half-max values
on either side and have amplitude and FWHM pulse width.

Question whether your best solution is a high end oscilloscope
with adequate vertical bits and BW, and use 'scope math to
pull your numbers. Certainly my old TDS3054 seems almost
capable by the numbers - 500MHz channel BW, 5GHz sample
and that's came-with-floppy-drive vintage (and 8-bit vertical).
Modern is 12 bits and at least double the BW.

No idea what "digital delay lines" are capable of these days.
Or what source-referenced timebase you might have available,
to delay from.

 

[KlausST]

Hi,

I'm not familiar with PLLSs, so I have been searching to understand and do what you suggest. But, I couldn't figure it out how can I use output frequency of 255/256? Using a divider?

Many PLLs have input dividers and outout dividers .... --> to get the "x/256"
And usually PLLs have a divider at the feedback. It acts like a multiplier ... --> to get the "255/x"

Klaus