Challenges with eFPGA Data Processing in My Current Setup

Tim12368

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I'm working on a project where I’m using an eFPGA to handle some real-time data processing tasks. The goal is to offload specific computations to the eFPGA to enhance performance.

The main issue I’m facing is with the data transfer between the eFPGA and the main processor. I’ve set up DMA to facilitate this, but I’m not achieving the expected data throughput. Specifically, I’m encountering problems with inconsistent data rates during transfer and difficulties in synchronizing the clock between the eFPGA and the processor. The timing mismatches are causing delays, which is impacting the real-time performance I need.

I’ve tried adjusting the clock frequencies on both the eFPGA and the processor, experimented with different buffer sizes, and even looked into alternative transfer protocols like SPI instead of DMA, but the results haven’t improved much. It feels like I’m missing something critical in the setup.

Has anyone here worked with eFPGA in similar situations? I’m looking for any advice on what might be causing these issues or how to optimize the setup. Any tips or experiences would be greatly appreciated!
 

What can you simulate? The normal FPGA workflow is to reproduce and fix problems in simulation.
Trial and error on real hardware is often a waste of time.
 
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