CGS vs VGS Plot

The below Edaboard thread seems to indicate the 32mosfets website is kaput. See post #13 which gives an alternate link to instructions for Cadence.

www.edaboard.com/threads/plot-gm-gds-vs-gm-id.389809

When a linkis dead , insert into web.archive.org


This covers some theory https://www.researchgate.net/public...jYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJfZGlyZWN0In19

A video search result


Keep in mind a Figure of Merit the product Tau= RdsOn * Cmax at some rating such as Vgs=2.5*Vt for std FETs , Vt = 2 to 4V and logic level FETs Vgs=2Vt is they tend to be constant but lower is best for speed.

In all cases in any family of FETs Cgs, Cds and Cdg all increase with lower RdsOn.
The same is true of bipolar diodes and transistors with variances with structural and material differences that affect voltage and thermal maxima. Thus SiC FETs have much lower Tau than Si FETs.

A spreadsheet with Tau * $ of thousands of different FETs downloaded from D-K vs a selection of Pivot Table variables for Y in a XY scatter plot gives very interesting results.

Thank you for providing good links. but i want to get the Vgs curve with respect to Cgs for checking capacitance behavior with respect to bias voltage, not frequency!

Yes mean this from the link.. Maybe it is better to ask the Cadence help Forum

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Also, do me a favour and ask how to plot Cgs vs RdsOn or Ciss vs RdsOn as Vgs has a 33% tolerance and I believe the product Ciss*RdsOn is very important.

Here they agree with me... https://www.shindengen.com/products/semi/column/basic/mosfet/what_are_mosfets.html



Then DM me or answer here if you find out.

Mucho gracias.
_. . . . . . .
|| Tony ||

p.s.
Conclusions
Qgs and Qgd do not mean what their names seem
to imply. Nevertheless they perform the useful
function of identifying together the amount of
charge necessary to bring the data-sheet-typical
MOSFET into full conduction.


Refs

In simulation you simply drive the gate from zero
with a pulsed current source recording Vgs and
dVgs/dt (or use Calculator deriv() ). That gives
you all you need for the equation of interest.

Whether this is useful might depend on what you
force or allow the drain to do. A good model would
cover the application-range. Knowing whether
yours is one....

Hi,
I think this might work in Cadence Virtuoso. Prepare a DC testbench to sweep the DC gate to source voltage and do a DC analysis. Go to the calculator, select OS parameter and select your device which must allow you to sweep an operating point parameter, which in your case would be Cgs. Send the expression to ADE and run the DC analysis and you should get a plot of Cgs vs Vgs.