CGS vs VGS Plot

[maria98]

hi, i want to plot Vgs voltage against Cgs capacitance. I find the link:

plot the curve of Cgs vs Vgs in Cadence

Hi. I want to check if the gate-source capacitance Cgs depends on bias voltage Vgs or not. I set up the circuit for simulation in Cadence as below. Could you tell me how can I plot the curve of Cgs vs Vgs. Thanks.

www.edaboard.com

but the attached document in the link is not working. Any one have info? thank you

 

[BradtheRad]

The below Edaboard thread seems to indicate the 32mosfets website is kaput. See post #13 which gives an alternate link to instructions for Cadence.

www.edaboard.com/threads/plot-gm-gds-vs-gm-id.389809

 

[D.A.(Tony)Stewart]

When a linkis dead , insert into web.archive.org

Plot gm and gm/Id - Cadence Tutorials

Gm is broadly used in analog design techniques. Gm can be noted or plotted very easily. Finding out gm for hand calculations at a given operating point Perform simple dc and transient analysis of a schematic comprising of a transistor of required W/L and applied Vds and Vgs. Now there are two...

web.archive.org

This covers some theory https://www.researchgate.net/public...jYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJfZGlyZWN0In19

A video search result

Keep in mind a Figure of Merit the product Tau= RdsOn * Cmax at some rating such as Vgs=2.5*Vt for std FETs , Vt = 2 to 4V and logic level FETs Vgs=2Vt is they tend to be constant but lower is best for speed.

In all cases in any family of FETs Cgs, Cds and Cdg all increase with lower RdsOn.
The same is true of bipolar diodes and transistors with variances with structural and material differences that affect voltage and thermal maxima. Thus SiC FETs have much lower Tau than Si FETs.

A spreadsheet with Tau * $ of thousands of different FETs downloaded from D-K vs a selection of Pivot Table variables for Y in a XY scatter plot gives very interesting results.

 

[maria98]

Thank you for providing good links. but i want to get the Vgs curve with respect to Cgs for checking capacitance behavior with respect to bias voltage, not frequency!

 

[D.A.(Tony)Stewart]

Yes mean this from the link.. Maybe it is better to ask the Cadence help Forum

.
Also, do me a favour and ask how to plot Cgs vs RdsOn or Ciss vs RdsOn as Vgs has a 33% tolerance and I believe the product Ciss*RdsOn is very important.

Here they agree with me... https://www.shindengen.com/products/semi/column/basic/mosfet/what_are_mosfets.html

Then DM me or answer here if you find out.

Mucho gracias.
_. . . . . . .
|| Tony ||

p.s.
Conclusions
Qgs and Qgd do not mean what their names seem
to imply. Nevertheless they perform the useful
function of identifying together the amount of
charge necessary to bring the data-sheet-typical
MOSFET into full conduction.

Refs

 

[dick_freebird]

In simulation you simply drive the gate from zero
with a pulsed current source recording Vgs and
dVgs/dt (or use Calculator deriv() ). That gives
you all you need for the equation of interest.

Whether this is useful might depend on what you
force or allow the drain to do. A good model would
cover the application-range. Knowing whether
yours is one....

 

[The_pearl]

Hi,
I think this might work in Cadence Virtuoso. Prepare a DC testbench to sweep the DC gate to source voltage and do a DC analysis. Go to the calculator, select OS parameter and select your device which must allow you to sweep an operating point parameter, which in your case would be Cgs. Send the expression to ADE and run the DC analysis and you should get a plot of Cgs vs Vgs.