riti
Member level 1
I have simulated clock buffer in fast process and trying to understand weird behaviour shown by cell.
Let's say I took transition time : Xns, load cap : YfF (very small cap).
With decrease in supply voltage , I have observed cell delay is decreasing, how is it possible?
On the other hand if I have increase the load cap but keep same transition time then I am seeing expected behaviour (cell delay increases with decrease in supply voltage )
Let's say I took transition time : Xns, load cap : YfF (very small cap).
With decrease in supply voltage , I have observed cell delay is decreasing, how is it possible?
On the other hand if I have increase the load cap but keep same transition time then I am seeing expected behaviour (cell delay increases with decrease in supply voltage )