CDR with half rate PD Question

[yli]

phase interpolator cdr

hi all:
Pardon my ignorance. I have a question about CDR, please give me some advice.
I have designed a 2.5G CDR with half rate PD. I follow the Razavi paper,
A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector, May 2001.

This CDR contains linear half rate PD, interpolation type ring VCO, charge pump and loop filter. I use the same architecture in the paper. All circuits simulate by Hspice.
I think that each block works well(maybe not).

However, when I connect each block together, the retiming data lose some bits. It will random lose a bit within random period.
In order to solve the question, first I get rid of the charge pump and loop filter. I directly input the correct VCO tuning voltage to make VCO oscillate at 1.25G. But the result is still incorrect. Then I replace the VCO to the ideal source(1.25G square wave) and I found that the retiming data is correct.

According to the situation, could I consider the VCO as a problem?
I think that the VCO may have bad phase noise. (I don't have software to do the simulation. or maybe it can be simulate at Hspice) Is that correct? or it results from other factors.

The VCO is a five stage interpolation ring oscillator.

In order to reduce the jitter, I try to make the waveform of VCO to be symmetric; therefore, I add the buffer amplifier(cherry hooper amplifier) in each stage.

Could someone give me some suggestion to solve this problem?
Thank you in advance.

 

[yli]

half-rate phase detector

hi all:
I try to refine my question.

The problem of my CDR circuit is that the Bit error rate is too large, which is 1e-3.
For the 2.5G CDR with half rate PD, it should be smaller than 1e-6 or even smaller.
I think that the problem would be result from the VCO.

I use the same VCO architecture in the Razavi paper, 10G CDR with half rate PD, May 2001.
I use the interpolation method to build up the each stage of VCO. The VCO contains five stage.
The interpolation method is an approach to let the signal to go through the fast path or slow path by controling the current. There is an extra delay cell in the slow path. I use the simple differential inverter to be the delay cell. The VCO can oscillate from 1.20GHz to 1.30GHz. The gain of VCO is around 100MHz/V.
Hspice is the simulation softwave I use.
I don't have the avaliable software to simulate the jitter and phase noise of VCO. Or does hspice can simulate the jitter or phase noise?

Could anyone give me some suggestion to correct the problem?

 

[layes2]

interpolating cdr paper

is that your recovery time not quick enough?

 

[gitarrelieber]

pd-question

Maybe you should measure the jitter of the VCO at locked status to decide whether the loss of data is attributed the phase noise of VCO.

You should definitively simulate the phase noise of the VCO. You can use PSS option of the simulator SpectreRF for fast buggeting of the phase noise of VCO. The simulation result is normally not so accurate. But you can at least get an idea of how good your VCO is.

At least you should hand-caculated the phase noise using Hajimiri's model.

 

[donlion]

cdr interpolation

i think maybe the PD does not work well.

 

[Sadegh.j]

half rate cell problem

Good Question, there can be several reasons:

1) The jitter of your VCO is too much, so some times, the data is not sampled properly.
2) The PLL response time is slow, so when the data changes, it takes a while for the system to adapt to the change.

Could you tell me how you designed your loop filter? I think this can be crucial.