CDAC layout

[the8thhabit]

Hi I am currently laying out a 10bit SAR ADC.
I am trying to layout the CDAC as shown in the picture on the left.
I have implemented the 10bit CDAC as shown in the first schematic below, where 1 determines the MSB and 10 determines the LSB.

My question is, when laying out the unitcap (15fF), will the CDAC mismatch be affected much if I lay it out like the picture I attached? (2nd picture)

If there are other layout methods, please share.

 

[sidun.av]

When doing the layout of such a small unit-size cap, interconnect parasitics play a slightly more important role. Anyway, if possible, it's better to stick to the common centroid layout pattern to reduce variation due to the oxide thickness variation.

 

[the8thhabit]

When doing the layout of such a small unit-size cap, interconnect parasitics play a slightly more important role. Anyway, if possible, it's better to stick to the common centroid layout pattern to reduce variation due to the oxide thickness variation.

Thank you!!
Does this mean you recommend a structure like the one below?

 

[sidun.av]

Thank you!!
Does this mean you recommend a structure like the one below?


View attachment 197857View attachment 197855

Yes, that one looks much better

 

[the8thhabit]

Can I ask for some ideas on how to layout the dummy capacitor in the CDAC layout?

And for a 10bit ADC, is it correct that I need 10 PADs for one ADC?
(1 bit allocated per 1 PAD)

 

[sidun.av]

And for a 10bit ADC, is it correct that I need 10 PADs for one ADC?
(1 bit allocated per 1 PAD)

Yes, this is correct if your output is parallel (each bit corresponds to a single wire).
If you want to reduce the number of pads, you would need to design SERDES and output interface (i.e. LVDS).

Can I ask for some ideas on how to layout the dummy capacitor in the CDAC layout?

I don't really understand what you mean. Usually, we simply short both of the plates and connect it to some stable potential (VDD/VSS).