[SOLVED] causes of bandgap fluctuations

[ella1923]

hi. id like to know the causes of output fluctuations of a bandgap with startup circuit..and how to solve this problem.

what are the things to consider when designing startup circuit for a bandgap?like
do i need long channel device or minimum length. how to design W/L for a startup circuit? is there a minimum current required in a startup circuit?

thank you.

 

[dick_freebird]

First, what kind of fluctuations? One part, output varies
over time? Or population of parts, with (say) a bimodal
distribution that's being caused by startup ckt bothering /
not-bothering the reference loop?

You need to get the diodes "lit" reliably, to some fraction
of the setpoint current but remove that influence once the
output is close to correct, and make sure it can't flicker
in and out based on noise or demand transients. That
kind of thing might make an "in-regulation" cutout cause
problems if transient out-of-regulation brings the startup
back online.

 

[ella1923]

thanks dick_freebird.

this is the only time i have tried to design startup circuit for bandgap. i understand
that it is important so that bandgap operates in a desired stable point. i have read
different forums here regarding how to test if startup circuit is working or not but i
get more confused.


regarding fluctuations, i am referring to the voltage output of my bandgap before it
settles to vref=1.17v. previous simulation, it took me about 500ms. right now,i got
this output on transient sim:




but i dont understand. i just followed instructions i have read in forums here. i ramp
vdd from 0 at different time.

when i checked my .lis file (by the way, i am using hspice)..all devices in my bandgap
are cutoff in time<7us. i am not sure if i have checked my startup circuit correctly,
if it is working or not.

without startup circuit and with fixed vdd=3.3v, my bandgap is working. when i ramp vdd
from 0, all devices are cutoff (bandgap and startup circuit). when i ramp vdd from 0
and when i add 7us after .op command,i.e., .op 7us, it shows in the .lis file that devices
are in saturation(except some devices of startup circuit). what does it means?i need to
make sure my startup circuit is working. please help.

thank you.

 

[dick_freebird]

The waveform is normal appearing. The initial overshoot
is probably just the supply ramp rate pushing through an
amplifier that's not closed-loop yet.

But this says only that the circuit has started, this time. The
mark of a good startup circuit is, that it starts -every-
time, all process & electrical & environmental and so on. That is
a more tedious chore to verify.

Saturation warnings probably come from when the supply
voltage is so low that many of the devices have no choice, but.
You might be interested in looking over the transient endpoint
for saturated devices and make sure you think none of them
are in critical places, where a gross error in modeling
of saturation behaviors might mess up stability or regulation.

 

[ella1923]

So the overshoot really happens initially when Vdd is ramp? This really occurs
for every bandgap with a startup circuit? :?

Does it means, we are required to have the least time to settle output to Vref?
The lesser the time, the better? :?

thanks.

 

[ella1923]

oh i understand now, at a certain time the startup circuit
provide a minute current to the bandgap circuit so that it
will prevent the bandgap to the undesired stable point. its
just that, i wasnt able to see the startup current graphically
from previous simulation. right now, we got our startup
current as 10nA at around 70usec. thank you very much.

 

[JoannesPaulus]

Unless you have an explicit spec on the bandgap start-up time, it can take several microseconds. Faster is not necessarily better in this case.
If you ramp up your suplly with a slower rate, you will see that the peaking will be lower.
Moreover, keep in mind that a power supply usually ramps up in hundreds of nanosecond...