I see your problems but you do not have a question or an expectation not being met.Here is a schematic containing a few cascaded 555 chips.
View attachment 190887The flow of the circuit is as follows:
a) When a push button across C16 is pressed, DELAY1 (555 configured as monostable) would cause delay depending upon the values of R2 + C1.
b) After the delay, TIMER1 (555 configured as monostable) gets triggered thru C12. Then TIMER1 would power on PULSES1 (555 configured as astable) for a duration depending upon the values of R3 + C3.
c) PULSES1 would generate pulses depending upon the values of R4 + R5 + C10.
d) When the TIMER1 duration is completed, PULSES1 gets off and DELAY2 is triggered thru C13.
The lower 3 x 555 are almost copy of the upper 3 x 555.
e) DELAY2 causes a delay then triggers TIMER2.
f) TIMER2 switches on PULSES2, which generates pulses.
The outputs are V-Cyl, Dir, Pulse and H-Cyl, each have an LED connected thru a current limiting resistor.
Theoretically the circuit seems OK, simulation is also OK. But physically, I am facing some problems:
a) If TIMER2 is present, there will be no output at DELAY2. (H-Cyl LED doesn't light up).
b) if TIMER2 is removed, DELAY2 will give output and H-Cyl LED would light up. Interestingly, PULSES2 also generates pulses though without TIMER2.
View attachment 190886
The values of the timing components, in the simulator are changed for speeding up the results.
OK. Then what would be the best way to overcome that issue. Tying up a zener at the 10K side would do?Be careful with supply decoupling, NE555s pulse current at the Vin pin as they change state.
However, there is a potential design flaw repeated three times. Look at the 100nF capacitors at the output of the first, third and fourth ICs, when the output of the NE555 is low, they charge to 10V through the following 10K pull-up resistor. When the output of a 555 goes high, it lifts the driven side of the capacitor high so momentarily the 10K side rises to about 20V and could damage the following IC or cause operational problems.
I have seen a similar system in a commercial tape deck I was asked to investigate. It worked for a while then died with ICs with holes blown through their tops! Not my design I promise.
Brian.
I thought, that was obvious, I simply want the circuit to perform without those problems.I see your problems but you do not have a question or an expectation not being met.
Share the sim. shortcut link and your expectation, s'il vous plais.
Thank you Dana.For Future reference this can be done easily, with more accurate timing :
View attachment 190901
Pulse Sequence Generator / Smart Timer
Often users, developers, hobbyists need timed and qualified event generators, many resorting to 555 timers and the like. The venerable 555 has had a long run but its limited in accuracy and capability. This approach uses block language to create...www.electro-tech-online.com
Regards, Dana.
The shortcut link is very lengthy.Share the sim. shortcut link and your expectation, s'il vous plais.
When TIMER2 is present, the voltage at pin 5 of DELAY2 is 4.78. No change when button is pressed.I believe it has to do with pin #5 and what voltage it adopts at the upper terminal of the capacitor (usually seen in schematics using a 555). I've applied a range of volt levels to pin 5 and seen the duty cycle respond. Also hi and low times.
I added a diode across R18, R19 and R20. No change in performance, the problem is still there.Using 555s at all isn't a good solution but the fix for the over-voltage problem is to add a diode across the 10K pull-up resistors so it dumps excess to the supply rail.
Brian.
When TIMER2 is present, the voltage at pin 5 of DELAY2 is 4.78. No change when button is pressed.
Without TIMER2, the voltage at pin 5 of DELAY2 is 4.90. When button is pressed it changes to 4.80.
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