Hey, I guess the illustration is all screwed up....well one terminal is the gate....and connect drain & source to bulk connected to VSS forms the other terminal (ofcourse - u now have a problem, a capacitance is formed only between a node a ground)
If you have control over the layout, you can get a better capacitor by placing the nmos transistor inside an NWell so that the bottom plate is all N type beneath the poly. Similarly for dual well processes put the pmos transistor inside a PWell