capacitor less LDO

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adeineira

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hi,
i want to ask about the capacitor less ldo
i have design the circuit,but the fast response circuit,but the quiscent current is high.. my question is the LDO is measured using operating quiescent current ? can you suggest an application for low voltage,high current ldo? my input voltage is 1.8V, iq=6mA, Vref=0.9V, Vout=0.9V ,cload=100pF, iload=0-100mA.. and then for the psrr, if the value of psrr is -20 and -60 ,which one is better ? is the quiescent current related to efficiency of the ldo,for example if the quiescent current is high the efficiency is low?
 

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Hi @adeineira
1. The response speed of your LDO is determined mostly by the BW of the amplifier. If you wish to use your LDO for high-frequency switching load (i.e. powering up a digital logic), then you would need a significant capacitor on the output of your LDO, to maintain fast current peaks from switching.
2. Quiescent current of an LDO is determined by the power consumption of the amplifier + resistive feedback current (you can reduce it by making your resistors in the feedback larger);
3. PSRR is usually inversely proportional to your amplifier gain and higher PSRR is better (-60 is better than -20).

P.S. 6mA is a huge quiescent current is too large even though your LDO is capless... You are basically burning your power doing absolutely nothing. I could recommend increasing the size of the feedback resistors while keeping an eye on stability.

Hopefully, that helps.
 

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Capless will impose a maximum output current dI/dt that
can be kept within error-band. Good for stable loads, not
so good for "steppy" ones.
 

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LDO dI/dt & dV/dt must exceed the load slew rate or else the load cap. is needed to meet your dV specs dV=Ic dt/C + dI*ESR.

Consider a CPU operating at 0.9 & 85W. Will an LDO be used? Not likely. Efficiency, step load regulation= Zout/load error%, ripple and cost are all tradeoffs with cost being the driving factor.
 

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from what i read ,if we want to design the fast transient or improved the overshoot and undershoot,there is a trade offf bettween the current and the transient response..is it correct?
 

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what do you mean by the load slew rate? dV/dt is the output ?
 

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adeineira said:
what do you mean by the load slew rate? dV/dt is the output ?
Click to expand...
I mean the BW of the error loop must well exceed the BW of the load to minimize error with enough gain, otherwise the BW of the Cap must do the same have BW = >10x to attenuate a step load with BW2=0.35/ dV/dt
 
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if my load is 100mA, is it ok if my operating quiescent current is 6mA?
[/QUOTE]

 

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A Quiescent Current that is 6% of the load current should be acceptable. IF this is within your power budgets/specifications, then why do you care.

But at the same time does it still burn 6mA at 0mA Load current? If it scales with the load, then you should be good to go.
Otherwise 6mA at No Load is an overkill.
Still if your application is such that you will never be at No Load, then I guess even 6mA is fine.


For the fast transient response you have to end up burning more power (to get higher bandwidth) OR area (larger internal capacitor to reduce over/under-shoots) OR a combination of both.

What is the end purpose of this LDO? What is it supplying power for? That will determine how much power/area you need to burn to get what you want.
If your load changes are slow i.e. does not have any fast transients, 6mA seems like a lot.
If your load changes fast, then you need a fast response LDO where you have different architectures that can be used to play around with to see what you want to sacrifice power or area or both.
 

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Step loads to/from 0 may cause problems like under/overshoot without an internal preload.

PSSR is dependent on f and load like this example. So the external cap to ground improves the PSRR with rising f dependent on ESR(?).

What specs do you want to compete with? Improve? compromise?


VIN PSRR​
VIN power-supply rejection ratio​
f = 100 Hz​
IOUT = 3 mA​
​
90​
​
dB​
IOUT = 300 mA73
f = 1 kHzIOUT = 3 mA84
IOUT = 300 mA75
f = 10 kHzIOUT = 3 mA70
IOUT = 300 mA60
f = 100 kHzIOUT = 3 mA53
IOUT = 300 mA43
f = 1 MHzIOUT = 3 mA65
IOUT = 300 mA​
​
27​
 

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adeineira said:
if my load is 100mA, is it ok if my operating quiescent current is 6mA?
Click to expand...
I don't think that this current scales with the load (because it is mainly coming from the resistive divider in your feedback, I presume), right?
Whether it is normal or not is mainly determined by your design specs, but I would consider it a bad design, because burning 6mA*1.8V = 10mW of power doing nothing doesn't sound good to me.
What will happen if you will reduce that current? Does your circuit go unstable or it cannot regulate properly?
 

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I suspect lowering the quiescent current will reduce the phase margin in his design from pole movement in the feedback loop. But 6% of the max load is a reasonable compromise if the fast gate loop produces very low error from the step line, and step load response.

I found a Master's paper from 2005 that summarized a 50mA, 2.8V, capacitor-less LDO voltage regulator fabricated in TSMC 0.35um CMOS technology. It consumed only 65uA of ground current with a dropout voltage of 200mV. However, it relies on low ESR input capacitance to improve step-line or PSRR. Pin inductance was reduced to 6nH. Output pin capacitance (low Zo)=sqrt(L/C) also improves step-load error.

-------------------


Note the above schemas are drawn differently. But they are the same in this simplified version.
Except the "Cap-less LDO" shows an Cint vs a bigger Cext+ESR for "conventional".
------------
TI's conventional LDO offering shows this with 1uF added to the output, so not quite capless but otherwise only 0.1 uF is needed.

 
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i did reduce the size of the cmos,but it is not reduce the current much,but it reduce the gain of the circuit . if the transistor is operate in subtreshold region,will it effect the bandwidth and the gain?
 

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adeineira said:
i did reduce the size of the cmos,but it is not reduce the current much,but it reduce the gain of the circuit . if the transistor is operate in subtreshold region,will it effect the bandwidth and the gain?
Click to expand...
Why do you reduce the size of your pass transistor? Of course it will reduce the overall gain (because it is a second gain stage after your amplifier) and might even limit the current capacity of your LDO. Moreover, it has nothing to do with your quiescent current.
I recommended increasing the size of feedback resistors, because this is what defines the quiescent current together with amplifiers' power consumption.
 

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