capacitor less LDO

Hi @adeineira
1. The response speed of your LDO is determined mostly by the BW of the amplifier. If you wish to use your LDO for high-frequency switching load (i.e. powering up a digital logic), then you would need a significant capacitor on the output of your LDO, to maintain fast current peaks from switching.
2. Quiescent current of an LDO is determined by the power consumption of the amplifier + resistive feedback current (you can reduce it by making your resistors in the feedback larger);
3. PSRR is usually inversely proportional to your amplifier gain and higher PSRR is better (-60 is better than -20).

P.S. 6mA is a huge quiescent current is too large even though your LDO is capless... You are basically burning your power doing absolutely nothing. I could recommend increasing the size of the feedback resistors while keeping an eye on stability.

Hopefully, that helps.

Capless will impose a maximum output current dI/dt that
can be kept within error-band. Good for stable loads, not
so good for "steppy" ones.

LDO dI/dt & dV/dt must exceed the load slew rate or else the load cap. is needed to meet your dV specs dV=Ic dt/C + dI*ESR.

Consider a CPU operating at 0.9 & 85W. Will an LDO be used? Not likely. Efficiency, step load regulation= Zout/load error%, ripple and cost are all tradeoffs with cost being the driving factor.

sidun.av said:

Hi @adeineira
1. The response speed of your LDO is determined mostly by the BW of the amplifier. If you wish to use your LDO for high-frequency switching load (i.e. powering up a digital logic), then you would need a significant capacitor on the output of your LDO, to maintain fast current peaks from switching.
2. Quiescent current of an LDO is determined by the power consumption of the amplifier + resistive feedback current (you can reduce it by making your resistors in the feedback larger);
3. PSRR is usually inversely proportional to your amplifier gain and higher PSRR is better (-60 is better than -20).

P.S. 6mA is a huge quiescent current is too large even though your LDO is capless... You are basically burning your power doing absolutely nothing. I could recommend increasing the size of the feedback resistors while keeping an eye on stability.

Hopefully, that helps.

Click to expand...

from what i read ,if we want to design the fast transient or improved the overshoot and undershoot,there is a trade offf bettween the current and the transient response..is it correct?

D.A.(Tony)Stewart said:

LDO dI/dt & dV/dt must exceed the load slew rate or else the load cap. is needed to meet your dV specs dV=Ic dt/C + dI*ESR.

Consider a CPU operating at 0.9 & 85W. Will an LDO be used? Not likely. Efficiency, step load regulation= Zout/load error%, ripple and cost are all tradeoffs with cost being the driving factor.

Click to expand...

what do you mean by the load slew rate? dV/dt is the output ?

adeineira said:

what do you mean by the load slew rate? dV/dt is the output ?

Click to expand...

I mean the BW of the error loop must well exceed the BW of the load to minimize error with enough gain, otherwise the BW of the Cap must do the same have BW = >10x to attenuate a step load with BW2=0.35/ dV/dt

sidun.av said:

Hi @ad
[QUOTE="sidun.av, post: 1782157, member: 689410"]
Hi [USER=690432]@adeineira
1. The response speed of your LDO is determined mostly by the BW of the amplifier. If you wish to use your LDO for high-frequency switching load (i.e. powering up a digital logic), then you would need a significant capacitor on the output of your LDO, to maintain fast current peaks from switching.
2. Quiescent current of an LDO is determined by the power consumption of the amplifier + resistive feedback current (you can reduce it by making your resistors in the feedback larger);
3. PSRR is usually inversely proportional to your amplifier gain and higher PSRR is better (-60 is better than -20).

P.S. 6mA is a huge quiescent current is too large even though your LDO is capless... You are basically burning your power doing absolutely nothing. I could recommend increasing the size of the feedback resistors while keeping an eye on stability.

Hopefully, that helps.

Click to expand...

if my load is 100mA, is it ok if my operating quiescent current is 6mA?
[/QUOTE]

sidun.av said:

eineira[/USER]
1. The response speed of your LDO is determined mostly by the BW of the amplifier. If you wish to use your LDO for high-frequency switching load (i.e. powering up a digital logic), then you would need a significant capacitor on the output of your LDO, to maintain fast current peaks from switching.
2. Quiescent current of an LDO is determined by the power consumption of the amplifier + resistive feedback current (you can reduce it by making your resistors in the feedback larger);
3. PSRR is usually inversely proportional to your amplifier gain and higher PSRR is better (-60 is better than -20).

P.S. 6mA is a huge quiescent current is too large even though your LDO is capless... You are basically burning your power doing absolutely nothing. I could recommend increasing the size of the feedback resistors while keeping an eye on stability.

Click to expand...

A Quiescent Current that is 6% of the load current should be acceptable. IF this is within your power budgets/specifications, then why do you care.

But at the same time does it still burn 6mA at 0mA Load current? If it scales with the load, then you should be good to go.
Otherwise 6mA at No Load is an overkill.
Still if your application is such that you will never be at No Load, then I guess even 6mA is fine.


For the fast transient response you have to end up burning more power (to get higher bandwidth) OR area (larger internal capacitor to reduce over/under-shoots) OR a combination of both.

What is the end purpose of this LDO? What is it supplying power for? That will determine how much power/area you need to burn to get what you want.
If your load changes are slow i.e. does not have any fast transients, 6mA seems like a lot.
If your load changes fast, then you need a fast response LDO where you have different architectures that can be used to play around with to see what you want to sacrifice power or area or both.

Step loads to/from 0 may cause problems like under/overshoot without an internal preload.

PSSR is dependent on f and load like this example. So the external cap to ground improves the PSRR with rising f dependent on ESR(?).

What specs do you want to compete with? Improve? compromise?