Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Capacitor layout in DACs

Status
Not open for further replies.

Yarrow

Member level 2
Member level 2
Joined
Jan 15, 2009
Messages
49
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Location
Norway
Activity points
1,699
Hi,

I am designing a charge scaling DAC. I was wondering what distance should be used between the capacitors in a capacitor array DAC? I imagine that using minimum distance between (poly-poly) capacitors is not ideal due to increase in the parasitic capacitance via the fringing capacitance?

Thanks in advance
 

You probably need 2 or more metal lines for the connectivity between the single PP-caps of the array, hence the P-P parasitic fringe capacitance between the individual caps won't matter - the top plates are far from each other, anyway. The metal wires' parasitics probably determine the achievable accuracy.

double_poly_capacitor.jpg
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top