Capacitor in pure digital process

Status
Not open for further replies.
H

hyy95120

Member level 1
Joined
Oct 21, 2005
Messages
38
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,522
why are they called sandwich caps?

Hi,
Has any one designed analog ckts in pure digital logic process? How do you handle the capacitor matching?
if there is no MIM or PIP available, what kind of caps do you use? How about using the interconnect layers? is the matching good for a 10bit ADC? How do you layout the caps?

Thanks a lot!
 

you can use fringer cap
 

Thanks for the reply!

what is fringer cap? is it also called comb cap?

How's the matching of such caps? is there a layout pic of such caps?

how about sandwich caps, is it good or bad?

Thanks!
 

There are lots of structure of finger cap. Comb is one of them.
For better matching, sandwich cap is prefered, but costs larger area.
 

why sandwich cap is preferred?

from this paper:
Capacity Limits and Matching Properties of Integrated Capacitors
By Roberto Aparicio, Ali Hajimiri,

The sandwich caps made by interconnect metals don't match well.



In the fab's matching report, only finger(comb like) caps are used. and the matching is not good.
2% for a 20-finger unit.

We need a 0.1% matching cap, if I put 20 units together, the total cap is too big (4pF).

My another question is, since I can put some unit caps in series and some in parallel to get the capacitance desired, how do i calculate the matching of such combination. is there a formula i can follow?

Thanks!
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…