Cap free LDO design for a wide output cap range?

[enno]

Hi,

I want to design a cap free LDO which is suitable to be used from pF to several uF output caps range.
Of course, ideally with less than 20 uA current consumption and good load transients.

But it seems to me that some works are only feasible to be used with several hundreds pF output caps( for example, robert j milliken's dissertation and Edward N. Y. Ho and Philip Mok's paper). It is quite difficult to reduce the frequency peaking and compensate the circuit with up to uF output caps.

Could someone give me some advices or recommend me some possible topology?

 

[enno]

Another question, it is said that the load transient depends on the bandwidth of the loop and the slew rate on the gate of the power device
I am wondering how can I figure out which factor is more dominant in each case?

 

[leo_o2]

Use comparator with offset to increase load response.

 

[enno]

thanks.

But I don't think I have really understood your point. Could you please explain me a little more?

Which two signals should be compared together with the comparator? and how this will increase the load response?

Use comparator with offset to increase load response.

 

[leo_o2]

Just use comparator to compare the two input signals for LDO error amplifier (output feedback voltage and reference voltage). If Vfb<Vref-offset, comparator outputs a signal to pull low LDO power PMOS.
Also another comparator (Vfb>Vref+offset) can be used for overshoot suppression.