Cap extraction of an IC PAD

[vlsi_design2]

Hi, I want to extract the capacitance of an IC PAD. Unfortunately there are no pins and I cannot pass lvs and do extraction. I may use a metal res to get a pin out and extract but are there better ways to do this?

 

[dick_freebird]

The below is based on a Cadence IC tools set....

You should be able to extract without LVS, "extract" is a precursor to
that. However you probably will need to contact the "bulk" to get the
bottom plate a net. May have to place a "bulk" polygon under a pad
instance, tap it, etc.? May need to "refine", maybe specifically enable
C parasitics extraction, depending on PDK architecture / vintage.

Try doing an extract on a copy of the pad cell, placed in a layout
set up to enable any of that kind of mysterious extraction related stuff
(identification layers and such). Then open the extracted, av_extracted,
analog_extracted view (whichever you can get). Turn off all layers
except instance/dwg. Now "select all". If extraction succeeded there
will be one or more itty bitty instance select markers, and you can
property-list-edit them in turn to see their values and connections.
The biggest will be the Met1-substrate, lesser ones are probably
metal-metal or fringing capacitors; those, you'd decide whether to
add to total pad capacitance or not, depending on where they lead.

--- Updated Jun 8, 2022 ---

Of course it might be well quicker to look at the PDK docs for
insulator thicknesses, form a mental image of a pad-stack
cross section (incl what it sits on which may have cut some
oxides, or not, repending on foundry*flow), and do the
Er*E0*A/t calculation.

Or even quicker if you have in the process library, a
pad/schematic alongside pad/symbol which holds a pacapacitor
with dimension-scaled, sane-appearing value, or points to an
actual pad model in the Spectre-pile.