[SOLVED] Can't understand my vhdl code error. Please help.

Hi everyone.
I've written a VHDL code to solve a special Genetic algorithm problem. But i get error and can't understand what causes the error. Can anyone show me the mistake(s)? Thanks.
The first error is appeared as: near 'gather_data': syntax error.

*****************

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED



entity tsp_module is
port(fsl:in std_logic_vector(0 to 31); opt_dist,c0,c1,c2,c3,c4,c5ut integer);
end;



architecture beh of tsp_module is

type int_array_1d is array(natural range <>) of integer;
type int_array_2d is array(natural range <> , natural range <>) of integer;
signal pathlen_org:int_array_2d(0 to 5,0 to 5);
signal path_org:int_array_2d(0 to 19,0 to 5);
signal st_signal:std_logic:='0';
signal comp:std_logic:='0';
signal final_path:int_array_2d(0 to 19,0 to 5);
signal final_fx:int_array_1d(0 to 19);


begin

process gather_data(fsl)
variable src1,src2,dst1,dst2:std_logic_vector(0 to 2);
variable dist1,dist2:std_logic_vector(0 to 4);
variable city0,city1,city2,city3,city4,city5:std_logic_vector(0 to 2);
variable path_number:std_logic_vector(0 to 4);
begin

****************

you havent named the proccess correctly. The format is

proc_name : process(sensitivity)

so you need

gather_data : process(fsl)

I also fear you are going to have more posts about things not working in the future (because of the use of math_real, comments about uniform function, lack of clock....)

Dear TrickyDicky
Thanks for the reply. I made a silly mistake in my code.