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Hello,
I have the following piece of code that i can simulate in libero. But when I go to compile it I get the error
"Can't find control signal for tmp"
I don't know how I would go by fixing it. Please help me out and thank you for your time.
I have the following piece of code that i can simulate in libero. But when I go to compile it I get the error
"Can't find control signal for tmp"
I don't know how I would go by fixing it. Please help me out and thank you for your time.
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
shiftdone : in std_logic;
powergood : in std_logic;
done : out std_logic;
reset : in std_logic;
Q : out std_logic_vector(15 downto 0);
K : out std_logic_vector(15 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(15 downto 0);
begin
process (C, CLR)
variable do : std_logic;
begin
if reset= '1' then
done <= '0';
do := '0';
else
if falling_edge(clr) then
k <= tmp;
done <= '1';
do := '1';
elsif (clr = '0' ) then
if do = '1' then
done <= '1';
else
done <= '0';
end if;
tmp <= "0000000000000000";
elsif (clr = '1') then
done <= '0';
if (C'event and C='1' and powergood = '1' ) then
tmp <= tmp + 1;
end if;
end if;
end if;
end process;
Q <= tmp;
end archi;