[PIC] Can't Figure out how to set 32MHZ Internal Oscillator for PIC16F1847

OSCCON = 0xF2; // INTOSC 32MHZ
[COLOR="#FF0000"]OSCTUNE = 0X1F; // MAX FREQUNCY[/COLOR]

5.2.2.3 Internal Oscillator Frequency Adjustment

The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator a change in
the OSCTUNE register value will apply to both.

The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.

When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.

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[COLOR="#FF0000"]OSCCON = 0xF2; // INTOSC 32MHZ[/COLOR]
OSCTUNE = 0X1F; // MAX FREQUNCY

OSCCON = 0x70;

OSCCON = 0xF0;

5.2.2.6 32 MHz Internal Oscillator Frequency Selection

The Internal Oscillator Block can be used with the 4X
PLL associated with the External Oscillator Block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:

• The FOSC bits in Configuration Words must be
set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).

• The IRCF bits in the OSCCON register must be
set to the 8 MHz HFINTOSC set to use
(IRCF<3:0> = 1110).

• The SPLLEN bit in the OSCCON register must be
set to enable the 4xPLL, or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.

Note: When using the PLLEN bit of the
Configuration Words, the 4xPLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.


The 4xPLL is not available for use with the internal
oscillator when the SCS bits of the OSCCON register
are set to ‘1x’. The SCS bits must be set to ‘00’ to use
the 4xPLL with the internal oscillator.

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6.0 REFERENCE CLOCK MODULE

The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR) and provide a secondary internal clock source
to the modulator module. This module is available in all
oscillator configurations and allows the user to select a
greater range of clock submultiples to drive external
devices in the application. The reference clock module
includes the following features:

• System clock is the source
• Available in all oscillator configurations
• Programmable clock divider
• Output enable to a port pin
• Selectable duty cycle
• Slew rate control

The reference clock module is controlled by the
CLKRCON register (Register 6-1) and is enabled when
setting the CLKREN bit. To output the divided clock
signal to the CLKR port pin, the CLKROE bit must be
set. The CLKRDIV<2:0> bits enable the selection of
eight different clock divider options. The
CLKRDC<1:0> bits can be used to modify the duty
cycle of the output clock(1). The CLKRSLR bit controls
slew rate limiting.

For information on using the reference clock output
with the modulator module, see Section 23.0 “Data
Signal Modulator”.

6.1 Slew Rate

The slew rate limitation on the output port pin can be
disabled. The Slew Rate limitation can be removed by
clearing the CLKRSLR bit in the CLKRCON register.

6.2 Effects of a Reset

Upon any device Reset, the reference clock module is
disabled. The user’s firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.

6.3 Conflicts with the CLKR pin

There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:

• LP, XT or HS oscillator mode is selected.
• CLKOUT function is enabled.

Even if either of these cases are true, the module can
still be enabled and the reference clock signal may be
used in conjunction with the modulator module.

6.3.1 OSCILLATOR MODES

If LP, XT or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
Section 5.2 “Clock Source Types” for more
information on different oscillator modes.

6.3.2 CLKOUT FUNCTION

The CLKOUT function has a higher priority than the
reference clock module. Therefore, if the CLKOUT
function is enabled by the CLKOUTEN bit in Configuration
Words, FOSC/4 will always be output on the port
pin. Reference Section 4.0 “Device Configuration”
for more information.

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