chyavanphadke
Newbie
I wrote a Verilog code for DE-10 Lite in Quartus Prime, I am getting the error it says "cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct". Can you please help?
Code:
module DemoBlink (
input clk, rst,
output [9:0] LED
);
reg [24:0] counter;
reg [9:0] temp;
initial begin
temp <= 1'b0;
counter <= 0;
end
always @ (posedge clk or posedge rst) begin
if (!rst) begin // Error is in this line
temp <= 1'b0;
counter <= 0;
end else begin
counter <= counter + 1;
if (counter == 8'd25000000) begin
temp = ~temp;
end
end
end
assign LED[0] = temp;
endmodule
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