cannot make accumulator-type DCO adjust output in phase

[cherishnguyen]

Hi all,

Who has been familiar with the Digital Phase Locked Loop plz help me!

Currently, I'm implement the DPLL, which has 3 main parts: Phase Detector, Accumulator-type DCO, and the Programmable Frequency divider.

According to document (klabs.org/mapld04/abstracts/sharma_a.doc), it says that: "With the accumulator-type DCO, the DCO output is generated by successively adding the value of an integer k to itself at the high frequency rate of a system clock fs.... The accumulation is done based on the incoming k value. This k value keeps changing every falling edge of the reference signal. The m.s.b of the accumulated output gives the DCO output signal. Based on this m.s.b a lead-lag signal is set and depending on the jitter condition a small portion of the N bits are taken out indicating the error or difference between the reference signal and the generated signal. This is scaled and given to a successive approximation block which modifies the value of k based on this value. The DCO continues accumulation using this new value of k and this way the DCO output always follows the reference signal.

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My problem is that I confuse how does Accumulator DCO keep the output in-phase with the input signal? As my understand, the k value is adjust to be added into. Accumulator just help to generate the output at the desired freq, that seems to me that it doesn't do anything to help PLL locked 2 signals in-phase as expect. I have read a lot but still don't find any DPLL describe how it generate the output in-phase with the reference freq. All they are concerned is how to increase or decrease the freq value. I wonder that is there any block like "phase shifter" that should be included in the design to keep 2 signals in-phase?

Anyone who knows about accumulator DCO plz give me your advices or ideas, anything will be helpful to me now!

 

[karesz]

Hi cherishnguyen,
I would sa; read please some web-articles over PLL,DPLL than DCOs and than implementations on FPGA.
You can find some classic PLL-books too..
This is a complex stof, but to learn & understand
Good luck!
K.

 

[RBB]

The output of your NCO needs to feedback into your phase detector. Thus the output of your phase detector adjusts your NCO phase & they will lock with time. Or am I mistaken in what you're asking?

 

[cherishnguyen]

The output of your NCO needs to feedback into your phase detector. Thus the output of your phase detector adjusts your NCO phase & they will lock with time. Or am I mistaken in what you're asking?

Thanks RBB,

My problem is that i wonder how an accumulator-DCO type can adjust k value to locked the output in-phase with the reference input, which both signals will drive to the Phase Detector.

I have tried to write the code to implement it, the DCO is simply an accumulator with one input is the feedback from its output, and the other is K value, which is not fixed as constant. K will be adjust to increase or decrease at every rising edge of the reference input by the controlller. But when i simulate it, changing k value just change the frequency value of output, and doesn't help anything to adjust the phase of output signal in an acceptable phase window. It's where i stuck, I have searched and read many document DPLL, which use the accumulator DCO or even another ways DCO implement such as increment-decrement counter ... but the only thing i found is that they mention about how to add carry pulse or remove borrow to change the frequency of output. Even they always say that 2 singals should be in-phase, but it seem that the design never reach locked (in-phase, and same freq) if they just do it by that way.

I know the Analog PLL they use capacitor in the VCO. Because some physical characteristics of capacitor device, it will help to change the phase of output basing on the voltage which is the phase difference between 2 signals. But for Digital PLL, the DCO is used instead of VCO. And my problem is as i described before.

I really need some helps from all of you. Whether i misundestand something about DCO's operation. i need someone will give me your advise.

Anyway, any replies will be meaningful for me now. Thx in advance.

 

[RBB]

The increase/decrease in frequency of the NCO IS a phase adjustment. Said another way as the NCO changes frequency, by speeding up or slowing down, it is actually changing its output phase.

 

[cherishnguyen]

The increase/decrease in frequency of the NCO IS a phase adjustment. Said another way as the NCO changes frequency, by speeding up or slowing down, it is actually changing its output phase.

Sorry RBB,

I'm talking about the Digital Controlled Ossilator, it is different from NCO you mentioned. Anyway, thx your reply.

 

[RBB]

How so?

 

[cherishnguyen]

How so?

Again RBB, I wanna know How the Accumulator DCO type work to adjust the ouput signal (in my case it is square signal) in-phase. NCO is another core that used to generate the Sinusoid signal at the desired freq, and phase precision. That is not what i want to implement with my DPLL to keep the output follow in-phase with input signal.

Do you have any recommend to me aobut Accumulator DCO? Please advice.