candence ams simulation: Verilog + VerilogA ?

[dongzz201]

How to do the ams simulation , using verilog + verilogA ?

Now My top cell is verilog file, in which the analog sub-module is instantiated.

1. The analog sub-module is SPICE netlist.
I can run the ams simulation.
The amsd block is :
include "./source/ana_cell.spi" ( SPICE netlist file )
amsd {
ie vsup=1.8
portmap subckt=ana_cell
config cell=ana_cell use=spice
}

2. The analog sub-module is verilogA file .

My amsd block is :
ahdl_include "./source/ana_cell.va" ( VerilogA file )
amsd {
ie vsup=1.8
}

Then the simulator always give me an error :
" Could not determine discipline for xx.xx.xx "

how to create the right amsd block ?

 

[noura7]

Hi,

i want to do the analog simulation with verilog-A simulator.
Can you please tell me where can i download a free verilog-A simulator?
thanks in advance.

Noura