can you suggest me an alternative to use clock both for reset and clocking purpose?

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kaushikrvs

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I am designing an I2C and want to use the SCL line as clock in one block and as an asynchronous reset in other block but the Lint checker throws a warning.
 

Hi,

please give more informations:
* are you designing a I2C master, slave or both?
* How are you designing? HDL? PLD, FPGA, ASIC, discrete logic?

***
I need to guess: (HDL and FPGA, I2C master)
Then you should have a high frequency master clock, where you generate SCL.
Then synchronize your SCL line (read back from IO) with this master clock...and then use this signal as synchronous RESET.

Klaus
 

its a slave I2C constructed in Verilog and I don't want to use SCL as IO; I want to use it as input itself and it should function as a reset for internal blocks.
 

Hi,

I want to use it as input itself and it should function as a reset for internal blocks.
Click to expand...

are you sure?
SCL is clocked with every transmitted bit. i´d say at least 18 times with the simplest data transfer.

So reset occurs 18 times.

And this is true even if another device is accessed via I2C.

What´s the idea behind this?

Don´t leave us in innocence:
PLD, FPGA; ASIC?
Do you have a master clock or not?

Klaus
 

Then please come up with a code for generation of start and stop bit of an i2c slave and explain it ?
 

if its a bad thing then please tell me how to code the start and stop bits if an i2c slave ?
 

Hi,

I think it´s YOUR job, not mine.
Nobody could write individual code for you, as long as you don´t provide exact specifications.
And you don´t answer the questions.

***
Please read I2C specification.
for generation of start and stop bit
Click to expand...
The slave (and thats what you are talking about) doesn´t need to generate start and stop bits. It has to recognize start and stop condition.
And start and stop condition isn´t clocked by the SCL, instead it is clocked (or better say it uses the edges) of SDA.

***
btw: Why don´t you use standard I2C IP?

Klaus
 
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