can you help me designing Charge Pump with error Amp

[movinghoon96]

Hello, I'm trying to design CP with error amp.

Vout is constantly rising by fast phase of Vref > VCO,

but error amp looks like 'reset' up/down output. So only small value increased.


Should I set common voltage for 'node x' at start?


+) Loop filter value was set by hand calculation.

 

[jjx]

Yes, it looks as if your output is killed.

Are you sure the amplifier is healthy? Polarity correct, etc?

Is the VCO loop closed per se, such that it actually strives towards it target value?

Is the slew-rate in par with your simulation times?

You can try with an ideal amplifier and/or inserting an initial value at X (actually better to put initial condition on your output capacitor(s)). That will immediately tell you if the amplifer misbehaves.

 

[movinghoon96]

Yes, it looks as if your output is killed.

Are you sure the amplifier is healthy? Polarity correct, etc?

Is the VCO loop closed per se, such that it actually strives towards it target value?

Is the slew-rate in par with your simulation times?

You can try with an ideal amplifier and/or inserting an initial value at X (actually better to put initial condition on your output capacitor(s)). That will immediately tell you if the amplifer misbehaves.

Thank you for reply.
1) I replaced my OPAMP with VCVS.
2) Set initial condition for OUTPUT to 2.5V

Simulation stopped itself by convergence error ( I'm not sure what it is )

(+) of OPAMP now works like discharging - regardless of UP/DOWN

 

[dick_freebird]

Might the functional problem have to do with "UP" really being "UPb" as far as the active sense of gate drive?

Is the "error amp" a behavioral or controlled source macro model by any chance? The source of the insane voltages must be found and fixed.

 

[movinghoon96]

Might the functional problem have to do with "UP" really being "UPb" as far as the active sense of gate drive?

Is the "error amp" a behavioral or controlled source macro model by any chance? The source of the insane voltages must be found and fixed.

1) Actually 'UP' should be down to turn on PMOS.

2) Yeah, peak voltage must be controlled
sadly I couldn't understand what you were talking about.
My OPAMP was simple 5-OTA, not verilog.

 

[dick_freebird]

Well, insane intermediate node voltages are coming
from somewhere and your debug can't proceed very
well, with that in place.

You might search around and see if gpdkXXX kits are
known for convergence problems (in the process
specific model cards) and if so any fixes / workarounds.

If you are getting blowup values from a handful of PDK
elements and nothing funny, that leans toward "bad kit".
But check that "nothing funny" supposition once more.
There will be a reason (or more) at the bottom of it all.

You could amuse yourself meanwhile by beating up
transistors, basic ID-VG and ID-VD curves taken over
more extreme ranges (including at least, reported values
from failed convergence) and see if you can identify an
unexpected, maybe nonphysical, result. Then you can
take that to whoever "owns" this kit, to tell you what is
going on.

You might want to make that connection now, maybe
this is known issue and a fresh kit could be had with
fewer problems. Because that's one thing about "contrib"
kits (especially ones which have no actual foundry to
tell them false from true) - you, the free lunch user, are
the free lunch front line QA resource. Have fun.