Can you explain this?

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ukint

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What will the outcome when the PMOS of inverter is connected to VSS and NMOS is connected to VDD? What would be the difference when compared to the operation of a normal inverter where PMOS is connected to VDD and NMOS connected to VSS

Thanks,
Ukint
 

If you search this forum, you'll find the answer. This question is asked every other month.
 

Can you help me with the url. I would greatly appreciate that
 

Here is the url for the site search. I'm not about to do your leg work for you, but it shouldn't take you more than 10 mins to find.
 

ukint said:
What will the outcome when the PMOS of inverter is connected to VSS and NMOS is connected to VDD? What would be the difference when compared to the operation of a normal inverter where PMOS is connected to VDD and NMOS connected to VSS

Thanks,
Ukint
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Mr.Ukint,

This configuration does not have any significance to use in Ckt design as i/p keep increases linearly your o/p also varies in the same fashion both transistors operate in cutoff condition , hence no o/p dirve so why do wanted to know this , but if you apply digital logic say 0 & VDD at i/p vthp and VDD-vthn at the o/p
Not only that you cann't layout this , so its just theoritical one
 

you.d better consult some semiconductor device structure and physics books.
 

It acts as a buffer , but the output voltage swing is limited to Vthp and Vdd-Vthn, since bothe the nmos and pmos are configured in source follower configuration
 

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