To run on chip variation(OCV), the timing library files need to contain information about derating factors(k). Not all library has this. If you turn on your OCV during timing analysis and your timing library does not have derating calculation, then the result is not valid for OCV analysis. The basic idea is same cell ( say for example NAND cell) may have different time for clk->Q on same chip at different location due to manufacturing process variation and other factors. That's why its called on chip variation. When you do timing analysis in bcwc, for setup, the analysis is done in worst corner and for hold, the analysis is done in best corner. However, Now, when you do timing analysis with on chip variation, based on chip variation % used in analysis, for setup, data path delay may be incremented by x% and clock path delay may be decrement by x% to account for onchip variation. You are basically preparing your design to not fail even if there is onchip variation.