Can you explain the difference between bc-wc and OCV in STA

[owen_li]

Hi.
I find bc-wc mode and ocv mode all use timing derate to model the pessimism.
So what is difference between the bc-wc mode and OCV mode in STA.
Thanks in advance.

 

[shelby]

bc-wc takes in two libraries and does setup on wcs and hold on bcs. OVC uses just one library for setup/hold, but you can always load more corners in multi-corner analysis.

bc-wc always uses slowest paths when doing setup checks. OCV can use fastest paths when doing setup checks, meaning it can speed up capture clock. Vice-versa for hold checks

 

[Mk.phnx]

Re: Can you explain the difference between bc-wc and OCV in

Both best case - worst case (bcwc) and OCV use two libraries -- Max and Min library (delay specific).
The difference is that bcwc strictly uses Max delay lib for setup analysis and Min lib for the Hold analysis while for OCV it considers both libraries in both the analysis depending upon the path i.e. For setup it uses the max library for data path and min for the clock path.
Vice Versa for hold analysis

 

[johanlo]

Re: Can you explain the difference between bc-wc and OCV in

OCV (On Chip Variation) tries to take care of local variations within a chip, while the different corners take cares of the whole range of variations from chip to chip. You usually use OCV for 65nm and smaller process nodes.

As explained before, for setup OCV uses the slow library for datapath and clock. BUT you set the clock path to be a bit more optimistic when it comes to delay, e.g. 10%. By doing this you are able to model local variations, where the data capture is done a bit earlier.

The OCV derate value is usually a rule of thumb, but it is possible to do statistical calculations based on the probablity for path x will fail.

 

[owen_li]

Re: Can you explain the difference between bc-wc and OCV in

Hi Mk.phnx

Can you confirm that OCV using two libraries to analyze timing ?

Shelby said that OCV just uses one libraries to analyze timing but multiple timing corner.

thanks all!

 

[Mk.phnx]

Re: Can you explain the difference between bc-wc and OCV in

Yes i am sure that ocv uses two different libraries. I've used ETS and done OCV analysis on it.

Regards

 

[madhuvallem]

here is good article related to the modes of analysis
https://solvnet.synopsys.com/dow_re...=advSearch&otSearchResultNumber=2&otPageNum=1

Yzou can go through it..

 

[ivlsi]

In PrimeTime, how can I enable either the WC-BC or OCV mode? How should I tell to the tool (PrimeTime) which analysis I want to do now?

Should I do separate runs for each one of the modes (totally 3 runs - wc, bc and ocv)?

---------- Post added at 23:00 ---------- Previous post was at 21:27 ----------

you set the clock path to be a bit more optimistic when it comes to delay, e.g. 10%

How can I do so? What command(PT) should I use?

---------- Post added at 23:04 ---------- Previous post was at 23:00 ----------

here is good article related to the modes of analysis
https://solvnet.synopsys.com/dow_ret...=2&otPageNum=1

Unfortunately, I cannot access the SolvNet. Could you please upload this article to the forum? thank you!

 

[yadavvlsi]

Check this:

 

[poluekt]

dmitryl, youn can select mode in PrimeTime:

set_target_library {worst.db}

set_min_library worst.db -min_version best.db
set_operating_conditions -analysis_type bc_wc -min best_cond -max worst_cond

or

set_operating_conditions -analysis_type on_chip_variation

Totally 2 runs.

 

[morris_mano]

To run on chip variation(OCV), the timing library files need to contain information about derating factors(k). Not all library has this. If you turn on your OCV during timing analysis and your timing library does not have derating calculation, then the result is not valid for OCV analysis. The basic idea is same cell ( say for example NAND cell) may have different time for clk->Q on same chip at different location due to manufacturing process variation and other factors. That's why its called on chip variation. When you do timing analysis in bcwc, for setup, the analysis is done in worst corner and for hold, the analysis is done in best corner. However, Now, when you do timing analysis with on chip variation, based on chip variation % used in analysis, for setup, data path delay may be incremented by x% and clock path delay may be decrement by x% to account for onchip variation. You are basically preparing your design to not fail even if there is onchip variation.

 

[vid31]

Hi morris_mano,

1)If I am using bc_wc mode,and also applying derate factor.set_timing_derate command to provide derates manually on clock and data path.Is that a valid?
2)If my design has lots of memories and more than one libraries than do I have to specify all these libraries and memories in set_min_library and set_operating_conditions?

Please help me with these.

Thanks & Regards,
Vid31

 

[zhanggd]

I just find in the latest PT, there is no bc_wc any more. Can someone explain why?