Can you explain property error in Lvs check?

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p.sivakumar

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property error

Hi guys

Can you explain property error in Lvs check?

Thanks
Siva
 

property error

hi,
when the transistor parameters like width and length are different from layout to schematic this error is displayed.
when you run lvs, the schematic netlist is compared to layout for netconnections and property of a transistors.
first when u run lvs,it extracts the layout and creates layout netlist file like .lsp and compares this .lsp to .sp.
.lsp is layout spice netlist and .sp is schematic spice netlist.
sometimes,due to incorrect connections of diffusions ,this error may occur.
 

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