doenisz
Junior Member level 2
Title.
I spent some time with this circuit, trying to tweak parameters for offset, kickback noise etc.
For a VDD of 0.8, I realized that when both inputs are like 751mV and 749mV, it could not charge neither OUTPB nor OUTNB enough to toggle the inverters. However, when it is 1.2V (just to try) and 300m, so that the "common-mode" is the same, it could make the decision correctly. Note that it's not about the differential voltage being huge either, since this comparator can easily detect 0.1mV differences when CM is around 300mV for example.
This led me to thinking, can we talk about common-mode input range for a strongarm latch? Or, is it about both inputs being high so that neither of the nodes are pulled-up high enough to get things rolling with the latching phase. But it's the initial dynamic amplification phase that's failing, so I can treat like the CM input range of an OPAMP?
Confused..
Thanks!
I spent some time with this circuit, trying to tweak parameters for offset, kickback noise etc.
For a VDD of 0.8, I realized that when both inputs are like 751mV and 749mV, it could not charge neither OUTPB nor OUTNB enough to toggle the inverters. However, when it is 1.2V (just to try) and 300m, so that the "common-mode" is the same, it could make the decision correctly. Note that it's not about the differential voltage being huge either, since this comparator can easily detect 0.1mV differences when CM is around 300mV for example.
This led me to thinking, can we talk about common-mode input range for a strongarm latch? Or, is it about both inputs being high so that neither of the nodes are pulled-up high enough to get things rolling with the latching phase. But it's the initial dynamic amplification phase that's failing, so I can treat like the CM input range of an OPAMP?
Confused..
Thanks!