Can we insert a process() into another process() in VHDL?

[rourabpaul]

can we insert a process() into another process(),where both has a same sensitivity list

 

[scanman]

Re: process in vhdl

Hi,

The answer is no. You can have multiple processes with same sensitivity lists in your entity architecture.
These processes all run concurrently. You can also break your code into components and install them into
your architecture where required. I find this works well as I can testbench each component separately and
then integrate them when fully de-bugged.
Here is good description of process:

**broken link removed**

scanman

 

[rourabpaul]

Re: process in vhdl

In previous thread you have given me a 12 bit modulus program with 'rst' input,but i want a continuous program without the 'rst' , i omit 'rst' from my program according to my logic,and its giving proper output,
could you post your 12 bit modulus program without 'rst'??

 

[scanman]

Re: process in vhdl

Can you post the modification you made (without the 'rst') ?
I am curious as to what you did.

 

[rourabpaul]

Re: process in vhdl

this is the file

 

[shanmugaveld]

Re: process in vhdl

It may work in simulation fine,in post simulation initial state of cs will be unknown and it may result in unexpected behavior.

 

[scanman]

Re: process in vhdl

So after the FPGA initializes the divider will start at 'Init' and then run continously.
This is fine as long as your data inputs and outputs are synched up correctly.
Otherwise you will need a way to synchronously 'Enable' the divider at the correct time and then
it can run continously.

 

[rourabpaul]

Re: process in vhdl

To scanman

you gave me a divider code where num and den are 8 bit and quo is 10 bit,i changed the generic value
in thi code but it do not give the desire result,
i attached the code and picture of the test bench output,
and also give be a code for remainder value of 12 bit, and it also do not give the desire result for some few value,i attached a picture of test bench,and the rdy out put is not high while the out put is ready

 

[scanman]

Re: process in vhdl

rourabpaul,

I have simulated the "remainder.doc" version with NUM = 29 and DEN = 3.
I get QUO = 9 and RDR = 2 with RDY output high (after 1 CLK).
There is a deliberate delay between QUO, RDR output and RDY output.
This is to make sure data is stable before RDY is asserted.
Try extending the time of your simulation to 1500ns and see if that works.
If this doesn't help I would need an exact specification of divider behaviour
in order to design what you need.

scanman

 

[rourabpaul]

Re: process in vhdl

In that case i want to know the clk frequency?
have you download it on fpga board?
actually i have 12 bit digital data which i want to encryoted where mod operation is very much needed,so i want to remove the rst input

 

[FvM]

Re: process in vhdl

It doesn't depend on the sensitivity list. According to the VHDL standard, a process
statement is a concurrent statement, that can't be placed in sequential code (
a process).

sequential_statement ::=
wait_statement
| assertion_statement
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement

concurrent_statement ::=
block_statement
| process_statement
| concurrent_procedure_call_statement
| concurrent_assertion_statement
| concurrent_signal_assignment_statement
| component_instantiation_statement
| generate_statement

P.S.: I've been confused by the new thread display and answered an old post. It had been already answered, of course.

 

[scanman]

Re: process in vhdl

In that case i want to know the clk frequency?
have you download it on fpga board?
actually i have 12 bit digital data which i want to encryoted where mod operation is very much needed,so i want to remove the rst input

Clock frequency = 50Mhz.
Yes, I have run the divider on Spartan 3E FPGA in a "Center of Mass" algorithm with good results.
I have been looking at making a pipelined version of this divider.
All you may need is a "Start" or "Enable" input to the divider to just start it in synch with your data.
After this it just runs continously until you "Stop" it. So, you need to start it running just as initial data
is available.
Is the data arriving continously in a consistent time frame?

scanman

 

[rourabpaul]

Re: process in vhdl

How can i start the process when the data is available or it changed?(removing rst)
what will be the syntax?
pls help

 

[scanman]

Re: process in vhdl

It may be possible to check data in Idle state.
You will need to store last values of NUM (last_NUM) and DEN (last_DEN).

when Idle => -- Idle state

if last_NUM /= current_NUM OR last_DEN /= current_DEN then -- Data has changed?

last_NUM <= NUM; -- Store new values
last_DEN <= DEN;
RDY <= '0';
SGN <= '0';
Error <= '0';
CS <= Init; -- Start new division cycle​

else

CS <= Idle;​

Do you have any signal from your data acquisition when your NUM, DEN is ready?
This would be the simplest way to synch and start the division.

scanman

 

[rourabpaul]

Re: process in vhdl

To Scanman
thank you for your help,
now i have made these two codes which are giving my desire results,
in "12bit_without_rst_modulus.doc" file i have change the RDR output,
in "12bit_without_rst_modulus.doc" where the RDR output is unchanged
dose not giving the proper result when i change the NUM zero to a positive value,
when the NUM is zero then RDR is also zero,but when i just change the zero value of NUM to a positive value in gives RDR=RDR+DEN,
say i give NUM=0, DEN=5, then RDR=0,
but when change the NUM as ,NUM=34(say),then RDR=4+5=9;
so i change the RDR output in my way in "12bit_without_rst_modulus.doc" file