matrixofdynamism
Advanced Member level 2
- Joined
- Apr 17, 2011
- Messages
- 593
- Helped
- 24
- Reputation
- 48
- Reaction score
- 23
- Trophy points
- 1,298
- Activity points
- 7,681
You could say that about any programming language - they all have libraries and associated best practices associated with them.But clearly SV wasnt good enough on its own, else UVM wouldnt have been created.
The OSVVM community has grown beyond 1200 members.There is the OSVVM library (osvvm.org) to try and address these problems, but it is not very widely used (it's trying).
Since we are moving towards ever complex designs year after year, does this not mean that since SystemVerilog with its advanced capabilities for verification is fully capable of functional coverage, we should now only emphasize SystemVerilog which can be used for synthesis as well as verification and do away with VHDL?
During the VHDL-2008 language revision, I look into what it would take to add Functional Coverage as language syntax to VHDL. Unfortunately, if we did a "me too" implementation of what SystemVerilog, it would require OO constructs (which VHDL almost has in Protected Types). We, the working group, decided to postpone implementing OO, so functional coverage as a language feature was shelved.There is no reason that VHDL couldn't have been enhanced to support these features, it's just that the EDA industry does not have the resources to support multiple verification languages. ...
Agreed, especially when adding language features. OTOH, with OSVVM, we have added functional coverage, constrained random, and intelligent testbenches to VHDL using open-source packages, hence, avoiding the cost to vendors. Vendors simply need to support enough of VHDL-2008 to implement the library.It takes a lot of engineering resources to develop, train, support and maintain the tools for each language, as well as the supporting infrastructure like Verification IP..
So while VHDL does not support functional coverage, the OSVVM libarary adds it in a form that is as concise as most language syntax.Can VHDL be used for "functional coverage"? Why not?
TrickyDicky,I think there are language feature limitations currently that still prevent full exploitation of VHDL as a full on verification language, namely:
1. Cannot have arrays of protected types.
2. Cannot pass access types into/out of a protected type (though this may be a good idea to maintain atomic access).
3. Generic packages cannot have variables in them. ...
4. Also, proper language defined support for binary file access would also help. Having to access a binary file via the char type is not portable as some simulators can behave differently.
3 is a bug. Did you report it? Be sure to speak to the person who is purchasing tool licenses to prioritize your language support requests. OTOH, protected types allow internal variables - what are you trying to create? Local instances of generic packages would also make a very simple transaction interface.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?