thverda
Newbie level 1
-- Company:
-- Engineer:
--
-- Create Date: 12:01:27 02/22/2013
-- Design Name:
-- Module Name: counter_shift - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity counter_shift is
port(
reset : in std_logic;
clk : in std_logic;
seg_output : out std_logic_vector( 7 downto 0)
);
end counter_shift;
architecture Behavioral of counter_shift is
signal cnt_8b : std_logic_vector ( 7 downto 0 );
signal seg_buf : std_logic_vector (7 downto 0);
signal segbuf_shift : std_logic_vector (7 downto 0);
signal shift_buf : std_logic;
signal cnt_4b : integer range 0 to 2;
begin
process ( reset,clk)
begin
if reset = '0' then
cnt_8b <= (others => '0' );
elsif rising_edge( clk ) then
cnt_8b <= cnt_8b + 1 ;
end if;
end process;
process (reset,clk,seg_buf,cnt_8b,segbuf_shift,cnt_4b,shift_buf)
begin
if cnt_8b = "11110001" then
seg_buf <= "10101100" ;-------
elsif reset ='0' then
--seg_buf <= (others => '0');
segbuf_shift <= (others => '0');
-- cnt_4b <= 0;
else
shift_buf <= seg_buf(0) ;
seg_buf(7) <= seg_buf(0);
seg_buf(6 downto 0) <= seg_buf(7 downto 1);
----------------------------------
segbuf_shift(7) <= shift_buf;
segbuf_shift(6 downto 0) <= segbuf_shift(7 downto 1);
--cnt_4b <= cnt_4b + 1;
end if; end process;
--process ( reset,clk,cnt_4b,segbuf_shift) ---------latch
--begin
-- if cnt_4b = '8' then
-- seg_output<=segbuf_shift; ----------segbuf_shift
--end process;
end Behavioral;
----------- i tryed to make waveform. follow this site.
https://cafe.naver.com/veryveryverilog/10
what is my problem?
i commended that
restart
run 1ms
but it stopped .
anyone hele me
i dont know why.
-- Engineer:
--
-- Create Date: 12:01:27 02/22/2013
-- Design Name:
-- Module Name: counter_shift - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity counter_shift is
port(
reset : in std_logic;
clk : in std_logic;
seg_output : out std_logic_vector( 7 downto 0)
);
end counter_shift;
architecture Behavioral of counter_shift is
signal cnt_8b : std_logic_vector ( 7 downto 0 );
signal seg_buf : std_logic_vector (7 downto 0);
signal segbuf_shift : std_logic_vector (7 downto 0);
signal shift_buf : std_logic;
signal cnt_4b : integer range 0 to 2;
begin
process ( reset,clk)
begin
if reset = '0' then
cnt_8b <= (others => '0' );
elsif rising_edge( clk ) then
cnt_8b <= cnt_8b + 1 ;
end if;
end process;
process (reset,clk,seg_buf,cnt_8b,segbuf_shift,cnt_4b,shift_buf)
begin
if cnt_8b = "11110001" then
seg_buf <= "10101100" ;-------
elsif reset ='0' then
--seg_buf <= (others => '0');
segbuf_shift <= (others => '0');
-- cnt_4b <= 0;
else
shift_buf <= seg_buf(0) ;
seg_buf(7) <= seg_buf(0);
seg_buf(6 downto 0) <= seg_buf(7 downto 1);
----------------------------------
segbuf_shift(7) <= shift_buf;
segbuf_shift(6 downto 0) <= segbuf_shift(7 downto 1);
--cnt_4b <= cnt_4b + 1;
end if; end process;
--process ( reset,clk,cnt_4b,segbuf_shift) ---------latch
--begin
-- if cnt_4b = '8' then
-- seg_output<=segbuf_shift; ----------segbuf_shift
--end process;
end Behavioral;
----------- i tryed to make waveform. follow this site.
https://cafe.naver.com/veryveryverilog/10
what is my problem?
i commended that
restart
run 1ms
but it stopped .
anyone hele me
i dont know why.