Yes, they can. But not at the same time. From STA point of view it is very common to have several clocks defined on the same point (port). But, you don not need to check/optimise timing path between such clocks.
You will have some muxing logic at top level which will control the clocks. You can have multiple clocks enter through same port, physically there will be only one clock at a time. So there will be a physically exclusive relation defined between clk1 and clk2 if you check the constraints