Can there be cases where an if else statement is outside an always block?

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Can there be cases where an if else statement is outside an always block?
 

Re: if else statement outside the always construct

Many.

In an initial block, function or task, generate block, constraint, ...
 

Re: if else statement outside the always construct

How can an if-else be inside a constraint? Can you please provide an example?

We always see if-else statement to be present inside an always statement.

Can if-else statement be written without an always statement inside functions or tasks?

Can case statement be written without an always statement inside functions or tasks??

Can case statement be outside an always block?

Thank you for replies.

Regards
 

Re: if else statement outside the always construct

See section 18.5.7 if-else constraints if the 1800-2012 LRM

It might help to explain where your doubts are coming from?
 

Re: if else statement outside the always construct

dave_59 said:
See section 18.5.7 if-else constraints if the 1800-2012 LRM

It might help to explain where your doubts are coming from?
Click to expand...
Hello

Right now I do not have the LRM in front of me. Can you please yourself explain in that case?

Regards
 

Re: if else statement outside the always construct

May I suggest the free IEEE Get program:
 

Re: if else statement outside the always construct

dave/FVM

Can there be cases where if-else statement be written outside an always block where the if-else in neith inside an initial block nor inside function,task, generate block?

Regards
 

Re: if else statement outside the always construct

Not prior to SystemVerilog.
But with SystemVerilog you can have

Code: 
class A
rand bit [7:0] len;
rand enum {big,middle,little} mode;
constraint c {if (mode == little)
                    len < 10;
                   else if (mode == big)

                   len > 100;}
endclass
 

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