Can somebody help me in designing dynamic comparator for pipeline ADC

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nari reddy

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hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline ADC in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-ADC..

I have several questions..

1) How to choose the value of Vrn and Vrp?

2) How to select the W/L value for each Nmos and Pmos transistor?

Please help me out

THank YOu!
 

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