Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Can somebody help me in designing dynamic comparator for pipeline ADC

Status
Not open for further replies.
N

nari reddy

Newbie level 2
Newbie level 2
Joined
Feb 5, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,295
hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline ADC in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-ADC..

I have several questions..

1) How to choose the value of Vrn and Vrp?

2) How to select the W/L value for each Nmos and Pmos transistor?

Please help me out:)

THank YOu!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top