Dear horace...
As per ur example, out of n no of lighting control units, any one sends recessive bit during ack slot, how the transmitter comes to know that particular node failed? Bcoz the other nodes may send successful ack, due to dominant nature, the recessive bit which is transmitted from the failed node, also represented as success to the transmitter. Am i right?
I wanted to know whether the receiver will monitor the bus during ack slot or not? bcoz the document explanations are like transmitter will monitor the bus during transmission. But nowhere they mentioned as the receiver monitors the bus during ack slot.
Anyway the document which u have given is nice to read. Thanks