Can memory arbiter be realized with combinational logic?

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Hi all,
Can memory arbiter be realized with combinational logic or it cumpolsarily be sequential logic. Please explain.

Best Regards,
 

Re: Memory arbiter

You willl usally find this as a sequential logic because of the timing constraints of the memory ( usally memories don't operate at the speed of your digital logic) But if you are using SRAM then may be you could go for purely combinational logic . It all depends on the speed of your memory blocks please go through the data sheet of your memory then u will be in a better shape to decide what needs to be done.
 

Re: Memory arbiter

Basically, comb logic and sequential logic is the same except that the timing is different. Therefore, you can implement in both depending on you timing budget of you design. If your design is not timing critical, just use comb logic since it is simple and gains in area and power.

For logic design, there are two things that you will concern. One is throughput. The other is latency. Your constrain is system requirment and area. Good design always has a good trade of between performance and area.
 

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Memory arbiter

Only the most trivial of arbitration schemes can be implemented with combinatorial logic.
 

Memory arbiter

Hi,
yes as lucano suggested the problem i am facing is with respect to latency. Now my controller puts a address on the address bus and expects the data in the next cycle but with a sequential arbiter I get 2 cycle delay as the address passes from controller to arbiter and then data from flash to controller through arbiter both consume one extra cycle so the whole logic goes for a six. So can anyone suggest what to do in that case. I can't insert wait states for every cycle as it will slow down the process a lot

Best Regards,
 

Re: Memory arbiter

If additional cycles could not be inserted for your system requirment you could just use the comb logic. The typical case is you have a CPU and a lot of peripherals. Just use pure comb logic on high address for Chip Select signal for each of your peripheral. In most cases, the peripherals are seamless to the processor. Therefore, you don't need the re-budget the timing. The data bus can be conneted directly to different peripherals.

Don't worry about the driving ability of the data bus. Even the processor but will drive a lot of peripheral bus you could solve the driving problem by adding the buffer branch to 4~6 peripherals each.
 

Memory arbiter

Compared with nomal arbiter, what is special for memory arbiter ?
 

Memory arbiter

I just curious about how to realize a round-robin arbiter in pure combinational logic. and make it synthesisable.

the key problem is the timming loop occurs in this circuit. which make synthesis tools hard to work
 

Memory arbiter

round-robin arbiter is same as others...

MUX bank, the select pin is controlled by your control logic, comb or seq, depending on your timing budget and timing reqirement. In your case, often a count and some comb logic for the control logic.

Draw a timing diagram you get it.
 

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