Can IBIS model simulate a full chip?

Can IBIS model simulates a full chip?

Hello,

I am simulating a full PCB. But the information of some chips are only provided in IBIS format.

Therefore, I need to simulate the full chip in order to find all the signals in the PCB. According to how IBIS models are generated, as long as I have the parameters for the IBIS input buffer model and IBIS output buffer model, and with the logical diagram for the chip, can I simulate the full chip in the PCB?

Thanks.

What do you mean by simulate full chip? Do you mean, simulate the internal parts like the logic inside?
The purpose of IBIS models is to provide a way to simulate the IO buffers of a device. It is an alternative to SPICE models which have certain drawbacks, among them being that they expose information that may otherwise be proprietery on how the buffers are implemented by a manufacturer. Why don't you post this question on eevblog and electronics.stackexchange also?

You are confusing different levels of abstraction, where each level needs a different tool.

IBIS is used to simulate the signal integrity issues, i.e. the analogue behaviour of tracks and packages with signals that will (typically) be interpreted as digital signals. Suitable tools inclde spice and other analogue simulators.

Once the signals have appropriate levels of integrity and will be correctly interpreted, you switch to simulating in the digital domain, using your HLL of choice, typically Verilog or VHDL.

If you try to mix abstraction levels, you will eventually end up trying to boot an o/s kernel using a spoice simulator. The only people that might try that are CPU designers, e.g. Intel.

Thanks for the reply.

The problem I am trying to solve is a PCB on a platform (like aeroplane or missile), and the chip on PCB controls the aeroplane/missile. Now an electromagnetic wave is hitting on that platform. I use electromagnetic code to solve the voltage change on the input of the chip on the PCB.

To understand how the wave affects the aeroplane or missile, I must know the response change at the output of the chip. The problem is, I only have the IBIS models of the chip. So is there a way to do the simulation only with the IBIS models?

There are too many variables to answer that question, e.g. frequencies, power, polarisation, angle of arrival, PCB track geometry, time of arrival, and many more.

Your approach should be via "electromagnetic compatability" (EMC), not digital/analogue simulation.

tggzzz said:

There are too many variables to answer that question, e.g. frequencies, power, polarisation, angle of arrival, PCB track geometry, time of arrival, and many more.

Your approach should be via "electromagnetic compatability" (EMC), not digital/analogue simulation.

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There is no need to separate EMC and circuit simulation. It is a hybrid simulation of wave physics and circuit physics. All the things you mentioned, frequency, power, phase, geometry, time delay could be dealt with properly in electromagnetics. I can decompose the problem into electromagetic part and circuit part, simulate them separately and coupled them in a domain tearing and connecting method. Nevertheless, what I am concern about is the proper simulation of the chip.

ultracalibur said:

There is no need to separate EMC and circuit simulation. It is a hybrid simulation of wave physics and circuit physics. All the things you mentioned, frequency, power, phase, geometry, time delay could be dealt with properly in electromagnetics. I can decompose the problem into electromagetic part and circuit part, simulate them separately and coupled them in a domain tearing and connecting method.

Click to expand...

Go on and do it. Tell us your results when you are finished.

Nevertheless, what I am concern about is the proper simulation of the chip.

Click to expand...

Lookup and understand the concept of "combinatorial explosion", particularly when digital circuits are involved.